REV. 0

AD5303/AD5313/AD5323

–4–

2mA

2mA

50pF

TO

OUTPUT

PIN

+1.6V

Figure 1. Load Circuit for Digital Output (SDO) Timing Specifications

SCLK

SYNC

DIN*

DB15

DB0

LDAC

LDAC

CLR

*SEE PAGE 12 FOR DESCRIPTION OF INPUT REGISTER

Figure 2. Serial Interface Timing Diagram