AD5322 datasheet(3/16 Pages) AD

3 / 16 page

REV. 0

–3–

AD5302/AD5312/AD5322

AC CHARACTERISTICS

1 (VDD = +2.5 V to +5.5 V; RL = 2 k

to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless

otherwise noted.)

B Version

Parameter

Min

Typ

Max

Units

Conditions/Comments

Output Voltage Settling Time

VREF = VDD = +5 V

AD5302

µs

1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)

AD5312

µs

1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)

AD5322

µs

1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)

Slew Rate

0.7

µs

Major-Code Transition Glitch Energy

nV-s

1 LSB Change Around Major Carry (011 . . . 11 to 100 . . . 00)

Digital Feedthrough

0.10

nV-s

Analog Crosstalk

0.01

nV-s

DAC-to-DAC Crosstalk

0.01

nV-s

Multiplying Bandwidth

200

kHz

VREF = 2 V ± 0.1 V p-p. Unbuffered Mode

Total Harmonic Distortion

–70

VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

NOTES

1Guaranteed by design and characterization, not production tested.

2See Terminology.

3Temperature range: B Version: –40

°C to +105°C.

Specifications subject to change without notice.

TIMING CHARACTERISTICS1, 2, 3

Limit at TMIN, TMAX

Parameter

(B Version)

Units

Conditions/Comments

ns min

SCLK Cycle Time

ns min

SCLK High Time

ns min

SCLK Low Time

ns min

SYNC to SCLK Active Edge Setup Time

ns min

Data Setup Time

4.5

ns min

Data Hold Time

ns min

SCLK Falling Edge to

SYNC Rising Edge

100

ns min

Minimum

SYNC High Time

ns min

LDAC Pulsewidth

t10

ns min

SCLK Falling Edge to

LDAC Rising Edge

NOTES

1Guaranteed by design and characterization, not production tested.

2All input signals are specified with tr = tf = 5 ns (10% to 90% of V

DD) and timed from a voltage level of (VIL + VIH)/2.

3See Figure 1.

Specifications subject to change without notice.

(VDD = +2.5 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted)

SCLK

SYNC

DIN*

DB15

DB0

t10

LDAC

*SEE PAGE 11 FOR DESCRIPTION OF INPUT REGISTER

Figure 1. Serial Interface Timing Diagram

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