AD5222 datasheet(2/10 Pages) AD

2 / 10 page

–2–

REV. 0

AD5222–SPECIFICATIONS

(VDD = 3 V

10% or 5 V

10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40 C < TA < +85 C,

unless otherwise noted.)

Parameter

Symbol

Condition

Min

Typ

Max

Unit

DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)

Resistor Differential NL

R-DNL

RWB, VA = NC

–1

±1/4 +1

LSB

Resistor Nonlinearity

R-INL

RWB, VA = NC

–1

±0.4 +1

LSB

Nominal Resistor Tolerance

∆RV

AB = VDD, Wiper = No Connect, TA = 25°C

–30

+30

Resistance Temperature Coefficient

RAB/∆TVAB = VDD, Wiper = No Connect

–35

ppm/

°C

Wiper Resistance

W = VDD /R, VDD = 3 V or 5 V

100

Ω

Nominal Resistance Match

∆R/R

CH 1 to 2, VAB = VDD, TA = 25°C0.2

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Resolution

Bits

Integral Nonlinearity

INL

RAB = 10 kΩ, 50 kΩ, or 100 kΩ

–1

±1/4 +1

LSB

INL

RAB = 1 MΩ

–2

±1/2 +2

LSB

Differential Nonlinearity

DNL

–1

±1/4 +1

LSB

Voltage Divider Temperature Coefficient

∆V

W/∆T

Code = 40H

ppm/

°C

Full-Scale Error

VWFSE

Code = 7FH

–1

–0.5

LSB

Zero-Scale Error

VWZSE

Code = 00H

0.5

LSB

RESISTOR TERMINALS

Voltage Range

VA, B, W

VSS

VDD

Capacitance

6 A, B

A, B

f = 1 MHz, Measured to GND, Code = 40

Capacitance

6 WC

f = 1 MHz, Measured to GND, Code = 40H

Common-Mode Leakage

ICM

VA = VB = VW

1nA

DIGITAL INPUTS AND OUTPUTS

Input Logic High

VIH

VDD = 5 V/3 V

2.4/2.1

Input Logic Low

VIL

VDD = 5 V/3 V

0.8/0.6 V

Input Current

IIL

VIN = 0 V or 5 V

±1

µA

Input Capacitance

CIL

5pF

POWER SUPPLIES

Power Single-Supply Range

VDD RANGE

VSS = 0 V

2.7

5.5

Power Dual-Supply Range

VDD/SS RANGE

±2.3

±2.7

Positive Supply Current

IDD

VIH = 5 V or VIL = 0 V

µA

Negative Supply Current

ISS

VSS = –2.5 V, VDD = +2.7 V

µA

Power Dissipation

PDISS

VIH = 5 V or VIL = 0 V, VDD = 5 V

150

400

µW

Power Supply Sensitivity

PSS

0.002 0.05

%/%

DYNAMIC CHARACTERISTICS

6, 8, 9

Bandwidth –3 dB

BW_10K

RAB = 10 kΩ, Code = 40H

1000

kHz

BW_50K

RAB = 50 kΩ, Code = 40H

180

kHz

BW_100K

RAB = 100 kΩ, Code = 40H

kHz

BW_1M

RAB = 500 kΩ, Code = 40H

7kHz

Total Harmonic Distortion

THD

A = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz

0.005

VW Settling Time

RAB = 10 kΩ, ± 1 LSB Error Band

µs

Resistor Noise Voltage

eN_WB

RWB = 5 kΩ, f = 1 kHz

√Hz

INTERFACE TIMING CHARACTERISTICS (Applies to All Parts)

6, 10

Input Clock Pulsewidth

tCH, tCL

Clock Level High or Low

CS to CLK Setup Time

tCSS

CS Rise to CLK Hold Time

tCSH

D to Clock Fall Setup Time

tUDS

D to Clock Fall Hold Time

tUDH

DACSEL to Clock Fall Setup Time

tDSS

DACSEL to Clock Fall Hold Time

tDSH

MODE to Clock Fall Setup Time

tMDS

MODE to Clock Fall Hold Time

tMDH

NOTES

1Typicals represent average readings at 25

°C, V

DD = 5 V.

2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 22 test circuit.

3Wiper resistance is not measured on the R

AB = 1 MΩ models.

4INL and DNL are measured at V

W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL

specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 21 test circuit.

5Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

6Guaranteed by design and not subject to production test.

DISS is calculated from (IDD × V DD). CMOS logic level inputs result in minimum power dissipation.

8Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.

The highest R value results in the minimum overall power consumption.

9All dynamic characteristics use V

DD = 5 V.

10See timing diagram for location of measured values. All input control voltages are specified with t

R = tF = 2.5 ns (10% to 90% of +3 V) and timed from a voltage level

of 1.5 V. Switching characteristics are measured using both VDD = 5 V or VDD = 3 V.

Specifications subject to change without notice.

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