AD28MSP01 datasheet(21/28 Pages) AD

21 / 28 page

AD28msp01

REV. A

–21–

Output Disable Time

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured out-

put high or low voltage to a high-impedance state. The output

disable time (tDIS) is the difference of tMEASURED and tDECAY, as

shown in the Output Enable/Disable diagram. The time,

tMEASURED, is the interval from when a reference signal reaches a

high or low voltage level to when the output voltages have

changed by 0.5 V from the measured output high or low volt-

age. The decay time, tDECAY, is dependent on the capacitive

load, CL, and the current load, iL, on the output pin. It can be

approximated by the following equation:

DECAY =

L × 0.5 V

from which

tDIS = tMEASURED – tDECAY

is calculated. If multiple pins (such as the data bus) are dis-

abled, the measurement value is that of the last pin to stop

driving.

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high-impedance state to when they start driv-

ing. The output enable time (tENA) is the interval from when a

reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram. If multiple pins (such as

the data bus) are enabled, the measurement value is that of the

first pin to start driving.

+ 0.5V

(MEASURED)

VOH

– 0.5V

(MEASURED)

REFERENCE

SIGNAL

OUTPUT

OH (MEASURED)

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS

VOLTAGE LEVEL TO BE APPROXIMATELY 1.5 V.

ENA

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

MEASURED

2.0V

1.0V

DECAY

(MEASURED)

t DIS

(MEASURED)

Figure 18. Output Enable/Disable

Serial Ports

Parameter

Min

Max

Unit

Timing Requirement:

tSCS

SDI/SDIFS Setup before SCLK Low

tSCH

SDI/SDIFS Hold after SCLK Low

Switching Characteristic:

tRD

SDOFS Delay from SCLK High

tRH

SDOFS Hold after SCLK High

tSCDH

SDO Hold after SCLK High

tSCDD

SDO Delay from SCLK High

SCLK

SDIFS

SDI

MSB

2ND MSB

3RD MSB

SDOFS

SDO

SCS

SCH

SCK

SCDD

SCS

SCH

SCDH

Figure 19. Serial Ports

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