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AD1887 датащи(PDF) 4 Page - Analog Devices

номер детали AD1887
подробное описание детали  AC??7 SoundMAX Codec
PDF  16 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD1887 датащи(HTML) 4 Page - Analog Devices

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REV. 0
–4–
AD1887–SPECIFICATIONS
CLOCK SPECIFICATIONS
*
Parameter
Min
Typ
Max
Unit
Input Clock Frequency
24.576
MHz
Recommended Clock Duty Cycle
40
50
60
%
POWER-DOWN STATES
Parameter
Set Bits
DVDD Typ
AVDD Typ
Unit
ADC
PR0
15.82
30.0
mA
DAC
PR1
15.08
26.3
mA
ADC + DAC
PR1, PR0
3.79
19.9
mA
ADC + DAC + Mixer (Analog CD On)
LPMIX, PR1, PR0
3.85
18.1
mA
Mixer
PR2
17.65
17.4
mA
ADC + Mixer
PR2, PR0
15.70
11.1
mA
DAC + Mixer
PR2, PR1
15.07
8.3
mA
ADC + DAC + Mixer
PR2, PR1, PR0
3.80
2.1
mA
Analog CD Only (AC-Link On)
LPMIX, PR5, PR1, PR0
3.85
18.1
mA
Analog CD Only (AC-Link Off)
LPMIX, PR1, PR0, PR4, PR5
0.06
18.1
mA
Standby
PR5, PR4, PR3, PR2, PR1, PR0
0.06
0
mA
Headphone Standby
PR6
17.66
26.1
mA
*Guaranteed but not tested.
Specifications subject to change without notice.
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
Typ
Max
Unit
RESET Active Low Pulsewidth
tRST_LOW
1.0
µs
RESET Inactive to BIT_CLK Startup Delay
tRST2CLK
162.8
ns
SYNC Active High Pulsewidth
tSYNC_HIGH
1.3
µs
SYNC Low Pulsewidth
tSYNC_LOW
19.5
µs
SYNC Inactive to BIT_CLK Startup Delay
tSYNC2CLK
162.8
ns
BIT_CLK Frequency
12.288
MHz
BIT_CLK Period
tCLK_PERIOD
81.4
ns
BIT_CLK Output Jitter
*
750
ps
BIT_CLK High Pulsewidth
tCLK_HIGH
32.56
42
48.84
ns
BIT_CLK Low Pulsewidth
tCLK_LOW
32.56
38
48.84
ns
SYNC Frequency
48.0
kHz
SYNC Period
tSYNC_PERIOD
20.8
µs
Setup to Falling Edge of BIT_CLK
tSETUP
5
2.5
ns
Hold from Falling Edge of BIT_CLK
tHOLD
5ns
BIT_CLK Rise Time
tRISECLK
246
ns
BIT_CLK Fall Time
tFALLCLK
246
ns
SYNC Rise Time
tRISESYNC
246
ns
SYNC Fall Time
tFALLSYNC
246
ns
SDATA_IN Rise Time
tRISEDIN
246
ns
SDATA_IN Fall Time
tFALLDIN
246
ns
SDATA_OUT Rise Time
tRISEDOUT
246
ns
SDATA_OUT Fall Time
tFALLDOUT
246
ns
End of Slot 2 to BIT_CLK, SDATA_IN Low
tS2_PDOWN
0
1.0
µs
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
tSETUP2RST
15
ns
Rising Edge of RESET to HI-Z Delay
tOFF
25
ns
Propagation Delay
15
ns
RESET Rise Time
50
ns
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
15
ns
*Output jitter is directly dependent on crystal input jitter.
Specifications subject to change without notice.



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