AD1885

–18–

REV. 0

Subsection Ready Register (Index 26h)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

h

6

2h

6

2 h

6

2 h

6

2h

6

2t

a

t

S

/

l

r

t

n

C

n

w

o

D

-

r

e

w

o

Pt

a

t

S

/

l

r

t

n

C

n

w

o

D

-

r

e

w

o

P

t

a

t

S

/

l

r

t

n

C

n

w

o

D

-

r

e

w

o

P

t

a

t

S

/

l

r

t

n

C

n

w

o

D

-

r

e

w

o

Pt

a

t

S

/

l

r

t

n

C

n

w

o

D

-

r

e

w

o

PD

P

A

ED

P

A

E

D

P

A

E

D

P

A

ED

P

A

E6

R

P6

R

P 6

R

P 6

R

P6

R

P5

R

P5

R

P 5

R

P 5

R

P5

R

P4

R

P4

R

P 4

R

P 4

R

P4

R

P3

R

P3

R

P 3

R

P 3

R

P3

R

P2

R

P2

R

P 2

R

P 2

R

P2

R

P1

R

P1

R

P 1

R

P 1

R

P1

R

P0

R

P0

R

P 0

R

P 0

R

P0

R

PX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XF

E

RF

E

R F

E

R F

E

RF

E

RL

N

AL

N

A L

N

A L

N

AL

N

AC

A

DC

A

D C

A

D C

A

DC

A

DC

D

AC

D

A C

D

A C

D

AC

D

Ah

x

0

0

0h

x

0

0

0

h

x

0

0

0

h

x

0

0

0h

x

0

0

0

Note: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the

AD1885 subsections. If the bit is a one, then that subsection is “ready.” Ready is defined as the subsection able to perform in

its nominal state.

ADC

ADC section ready to transmit data.

DAC

DAC section ready to accept data.

ANL

Analog gainuators, attenuators, and mixers ready.

REF

Voltage References, VREF and VREFOUT up to nominal level.

PR[5:0]

AD1885 Power-Down Modes. The first three bits are to be used individually rather than in combination with each

other. The last bit PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be

powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until

the reference is up.

PR0 – Power-Down ADC

PR1 – Power-Down DAC

PR2 – Power-Down Analog Mixer

PR4 – Power-Down AC-Link

PR5 – Power-Down Internal Clock

PR6 – Power-Down Headphone

EAPD – External AMP Power-Down Control Signal

PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can

either be up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are

both set.

In multiple-codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in

the slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5.

Power-Down State

EAPD PR6

PR5

PR4

PR3

PR2

PR1

PR0

ADC Power-Down

X

0

0

0

0

0

0

1

DAC Power-Down

X

0

0

0

0

0

1

0

ADC and DAC Power-Down

X

0

0

0

0

0

1

1

Mixer Power-Down

X

0

0

0

0

1

0

0

ADC + Mixer Power-Down

X

0

0

0

0

1

0

1

DAC + Mixer Power-Down

X

0

0

0

0

1

1

0

ADC + DAC + Mixer Power-Down

X

0

0

0

0

1

1

1

Standby

X

1

1

1

1

1

1

1

Extended Audio ID Register (Index 28h)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

h

8

2h

8

2 h

8

2 h

8

2h

8

2D

I

o

i

d

u

A

d

e

d

n

e

t

x

ED

I

o

i

d

u

A

d

e

d

n

e

t

x

E

D

I

o

i

d

u

A

d

e

d

n

e

t

x

E

D

I

o

i

d

u

A

d

e

d

n

e

t

x

ED

I

o

i

d

u

A

d

e

d

n

e

t

x

E1

D

I1

D

I 1

D

I 1

D

I1

D

I0

D

I0

D

I 0

D

I 0

D

I0

D

IX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XA

R

VA

R

V A

R

V A

R

VA

R

Vh

1

0

0

0h

1

0

0

0

h

1

0

0

0

h

1

0

0

0h

1

0

0

0

Note: The Extended Audio ID is a read only register.

VRA

Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio.

ID[1:0]

ID1, ID0 is a 2-bit field that indicates the codec configuration: Primary is 00; Secondary is 01.