AD1855

–13–

REV. B

Smooth Volume Control with Auto Ramp Up/Down

The AD1855 incorporates ADI’s 1024 step “Smooth Volume

Control” with auto ramp up/down. Once per L/

RCLK cycle,

the AD1855 compares current volume level register to the vol-

ume level request register Data 9 through Data 0. If different,

volume is adjusted 1 step/sample. Therefore a change from

max to min volume takes 1024 samples or about 20 ms as

shown in Figure 20.

20ms

TIME

–60

–60

0

0

VOLUME REQUEST REGISTER

ACTUAL VOLUME REGISTER

Figure 20. Smooth Volume Control

Output Drive, Buffering and Loading

The AD1855 analog output stage is able to drive a 1 k

Ω (in

series with 2 nF) load.

Power-Down/Reset

The AD1855 offers two methods for power-down and reset.

When the

PD/RST input (Pin 24) is asserted LO, the AD1855

is reset. As an alternative, the user can assert the soft power-

down bit (Data 13) HI. All the registers in the AD1855 digital

engine (serial data port, interpolation filter and modulator) are

zeroed. The two 8-bit registers in the serial control port are

initialized back to their default values. The user should wait

100 ms after bringing

PD/RST HI before using the serial data

input port and the serial control input. The AD1855 is designed

to minimize pops and clicks when entering and exiting the power-

down state. A reset should always be performed at power-on.

De-Emphasis

The AD1855 offers digital de-emphasis, supporting 50

µs/

15

µs digital de-emphasis intended for “redbook” 44.1 kHz

sample frequency playback from Compact Discs. The AD1855

offers control of de-emphasis by asserting the DEEMP input

(Pin 9) HI or by asserting the de-emphasis register bit (Data 12)

HI. The AD1855’s de-emphasis is optimized for 44.1 kHz but

will scale to the other sample frequencies.

Control Signals

The IDPM0, IDPM1, and DEEMP control inputs are normally

connected HI or LO to establish the operating state of the

AD1855. They can be changed dynamically (and asynchro-

nously to L/

RCLK and the master clock) as long as they are

stable before the first serial data input bit (i.e., MSB) is pre-

sented to the AD1855.