AD1672

REV. 0

–16–

Clock Input

A 49.9

Ω resistor (R9) terminates this input. Remove and/or

replace this resistor with other values in order to match different

cable impedances. An external sample clock must be provided

to the BNC connector labeled CLK (J5). The rising or falling

edge of CLK can be selected to trigger a conversion and is avail-

able to the user via the connector E1 by configuring S1 and S3.

The CLK INPUT has two modes of operation which is

determined by the position of S5. When S5 is in Position B, the

CLK is directly coupled to U5, a Hex inverter with Schmitt trig-

ger inputs. The requisite input levels are CMOS-compatible in

this mode. When S5 is in Position A, the CLK is ac coupled via

C23 and level shifted via R10, R12, and R13. This mode is

used to generate a low jitter clock input for the AD1672 with a

tunable duty cycle. The input to CLK (J5) is a filtered 5 V p-p

sine wave at the desired sampling frequency. The duty cycle

may be adjusted via R10.

S1

Selects the rising or falling edge of CLK to initiate a con-

version. When S1 is in Position A, the falling edge of

CLK is selected. When S1 is in Position B, the rising

edge of CLK is selected.

S3

Selects the rising or falling edge of CLK made available to

the user via the connector via E1, Pin 33. When S3 is in

Position A, the rising edge of CLK is selected. When S1

is in Position B, the falling edge of CLK is selected.

S5

Selects CLK INPUT mode of operation. If S5 is in Posi-

tion A, the low jitter, ac coupled mode of operation is se-

lected. If S5 is Position B, the dc coupled mode

of operation is selected.

Digital Inputs/Outputs

The digital outputs of the AD1672 are buffered and connected

to a 40-pin IDC connector (E1). The digital output can be ei-

ther in a straight binary or twos complement format by configur-

ing S2. S2 selects the MSB output or its complement. The

Out-of-Range (OTR) output is available on test point, OTR.

S2

Selects either the MSB or its complement for either

straight binary or twos complement digital output data

formatting, respectively. When S2 is in Position A, the

straight binary format is selected. When S2 is in Position

B, the twos complement format is selected.

Layout Considerations

Figure 31 to 34 show the schematic diagram, component layout,

trace routing, and silk screening for the AD1672 4-layer

evaluation board. Figure 35 and 36 show the AD1672 ground

and power plane layouts.

The AD1672-EB is a 4-layer evaluation board consisting of

separate ground and power plane layouts. Separate ground and

power planes have several advantages for high speed layouts.

(For further information outlining these advantages, see the

application note “Design and Layout of a Video Graphics Sys-

tem for Reduced EMI” [E1309] available from Analog Devices

[(617) 461-3392].) The ground planes are separated into ana-

log and digital planes that are joined together under the AD1672.

The AD1672 should be treated as an analog component and a

common ground connection should be made underneath the

AD1672 despite some pins being labeled “digital” and some as

“analog” ground plane.

A summary of the test point designators and a parts list is given

in Table VIII and IX.

Table VIII. Summary of Test Point Designators

Test Point

Description

TP1

AGND

TP2

AIN

TP3

TP4

TP5

TP6

DGND

TP7

CLK

Table IX. AD1672 EB Parts List

Reference

Value/Part Type

Package

Qty/Bd

U1

AD8047

8-Pin DIP

1

U2

REF192

8-Pin DIP

1

U3

DAC08

16-Pin DIP

1

U4

AD1672

28-Pin PLCC

1

U5

74HC14N

14-Pin DIP

1

U6, U7

74HC541N

20-Pin DIP

2

AIN, CLK

BNC JACKs

Small, Vertical

2

JP1–10

Headers/Shunts

2-Pin

10

S1-S5

SPDT, Secme

0.1"

× 0.3"

5

E1

40-Pin IDC

R.A., Male

1

Connector

w/Latches

R1, R9

50

Ω

1%, 1/4

Ω

2

R2–R4

499

Ω

1%, 1/4

Ω

6

R11–R13

R5

4.99 k

Ω

1%, 1/4

Ω

1

R6

100

Ω

1%, 1/4

Ω

1

R7, R8

2.49 k

Ω

1%, 1/4

Ω

2

R10

2.0 k

Ω POT

1%, 1/4

Ω

2

C1, C2, C4,

0.1

µF

Ceramic, SMT

11

C12–C16,

C18–C20

C3, C6–C9,

1.0

µF

Ceramic,

8

C11, C22, C23

Throughhole

C5, C17, C21

10

µF

Tantanlum

3

Throughhole

C10

0.01

µF

Ceramic

1

C24

47

µF

Alum. Elect.

1