AD1385 datasheet(14/20 Pages) AD

14 / 20 page

AD1385

REV. 0

–14–

Buffering the multiplexer’s output will eliminate the problems

caused by its ON-resistance. The choice of buffer depends on

the nature of the system’s input signals. There are two cases to

consider: static inputs and dynamic inputs.

“Static” Applications

Amplifier noise, CMRR linearity, and settling time are of pri-

mary importance when the inputs are low frequency or DC.

This is the case in a CAT-scan imager, for example, when sig-

nals are produced by integrating photocurrents. Noise limits

ultimate system resolution. The AD1385 has a typical input-

referred noise of 70

µV rms. Buffer noise must be added to this

in a root-sum-squares fashion to determine total system noise. A

buffer amplifier which adds noise of 18

µV rms, for example,

will result in a system noise level of (18

2 +702)1/2 = 72

µV rms, a

negligible increase. Detailed system noise calculations require

knowledge of the buffer’s noise spectral density and equiva-

lent noise bandwidth. The AD1385’s equivalent noise band-

width is 2.2 MHz. Low Noise Electronic Design (C.D.

Motchenbacher and F.C. Fitchen, John Wiley and Sons, New

York, 1973) provides excellent discussions of noise analysis and

calculations.

Buffer amplifier CMRR produces only gain error as long as the

value of CMRR is independent of signal level. The size of this

“gain error” is directly related to the actual value of CMRR; an

amplifier with 60 dB CMRR will create an apparent gain error

of 0.1%. The precise value of CMRR is not critical as long as it

remains independent of signal level. Any variation in CMRR

with input level will introduce nonlinearity. The smaller the

value of CMRR (in dB), the more critical variations in this value

become. An amplifier with CMRR ranging from 100 dB to

110 dB over the range of –10 V to +10 V will produce negligible

nonlinearity, while an amplifier whose CMRR varies from 60 dB

to 70 dB over the same range would be completely unacceptable.

Buffer settling time will affect the system’s throughput. The sys-

tem sample rate can be maintained at 500 kHz provided the

buffer’s settling time is less than about 1.7 microseconds. The

input channel should be switched just after the AD1385’s SHA

enters Hold mode as indicated by a rising edge at Hold Com-

mand In (Pin 22).

“Dynamic” Applications

Dynamic applications complicate the choice of buffer amplifier.

The amplifier’s harmonic distortion performance now becomes

as important as its noise, CMRR linearity, and settling behavior.

Few manufacturers specify amplifier THD in the noninverting

configuration. These specifications, when available, seldom ad-

dress signals greater than 10 V p-p or frequencies above 1 kHz.

It may be necessary to characterize candidate amplifiers from

several vendors to find the best fit to the amplitude and fre-

quency requirements of a particular application. Such evalua-

tions are easily performed using a spectrum analyzer. A notch

filter tuned to the fundamental frequency greatly improves mea-

surement resolution. It is also possible to use the AD1385 as

the measuring device by performing FFTs on the output data.

Refer to the discussion of signal sources in Testing the AD1385.

Unipolar Operation

The AD1385 does not provide a direct unipolar input capabil-

ity. Unipolar inputs can be achieved using the circuits of Fig-

ures 26 and 27. The circuit in Figure 26 is suitable when a low

input impedance is acceptable. The AD845 is an excellent am-

plifier choice for this application. Multiplexed applications

should use the circuit of Figure 27. The discussions under High

Impedance Inputs also apply to amplifier selection for high

impedance unipolar operation.

Figure 26. Unipolar-to-Bipolar Conversion (Low Input

Impedance)

Figure 27. High Input Impedance Unipolar-to-Bipolar

Conversion Circuit

Data Bus Interface

The AD1385’s data outputs are 4 mA CMOS drivers and are

not intended to be connected directly to a system data bus.

Charging and discharging a capacitive data bus creates large

supply transients and ground spikes which can interfere with

the AD1385’s operation and result in erroneous data. Registers

and/or buffers should be used to isolate the AD1385 from the

bus. Buffering devices should be located close to the AD1385 to

minimize the capacitive load presented to the converter’s data

outputs. Control will be simplified by permanently grounding

the AD1385’s OE input when using buffers. A schematic of a

typical 16-bit bus interface is shown in Figure 28.

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