REV. M

Page 27

September 1998

AS3502

#

Parameter

Symbol

Condition

Min

Typ

Max

Units

9

Hold Time from SCLK Low to

Short Strobe Low

tHCSSL

30

ns

10

Hold Time from SCLK Low to

Long Strobe High

tHCLSH

0ns

11

Set Up Time from Long Strobe

High to SCLK Low

tSLSCL

30

ns

12

Hold Time from 3rd Period of

SCLK Low to Strobe Low

tHCLSL

30

ns

13

Delay Time from SCLK High to

TXD Valid

tDCD

CL= 100 pF + 2 TTL Loads

80

ns

14

Delay Time to Valid Data from

TXS or SCLK whichever comes

later

tDSD

CL= 100 pF + 2 TTL Loads

80

ns

15

Delay Time from SCLK or TXS

Low to TXD Disabled

tDCZ

80

ns

16

Set Up Time from RXD Valid to

SCLK Low

tSDC

30

ns

17

Hold Time from SCLK Low to

RXD invalid

tHCD

20

ns

18

Strobe Pulse Frequency

fSTB

8

KHz

* Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing

Note 1: A 50:50 duty cycle must be used for 2.048MHz operation

Note 2: AS3502 provides a software programmable input clock divider that is programmable from 1:1 to 1:9

TXS, RXS

(LONG)

MSB

D

D

D

D

LSB

TXD

1

234

16

(8)

SCLK

TXS, RXS

(SHORT)

3

2

5

7

89

10

12

13

14

15

11

4

6

1

MCLK

RXD

MSB

D

D

16

17

PCM Timing Diagramme