CY8C54LP datasheet(62/117 Pages) CYPRESS

62 / 117 page

PRELIMINARY

PSoC® 5LP: CY8C54LP Family

Datasheet

Document Number: 001-84934 Rev. **

Page 62 of 117

11. Electrical Specifications

Specifications are valid for –40 °C

≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC

Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the “Example

Peripherals” section on page 37 for further explanation of PSoC Creator components.

11.1 Absolute Maximum Ratings

Note

Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to

maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above

normal operating conditions the device may not operate to specification.

Table 11-1. Absolute Maximum Ratings DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

TSTG

Storage temperature

Extended duration storage

temperatures above 100 °C

degrade reliability.

–55

100

°C

VDDA

Analog supply voltage relative to

VSSA

–0.5

–

VDDD

Digital supply voltage relative to

VSSD

–0.5

–

VDDIO

I/O supply voltage relative to VSSD

–0.5

–

VCCA

Direct analog core voltage input

–0.5

–

1.95

VCCD

Direct digital core voltage input

–0.5

–

1.95

VSSA

Analog ground voltage

VSSD – 0.5

–

VSSD +

0.5

VGPIO[11]

DC input voltage on GPIO

Includes signals sourced by VDDA

and routed internal to the pin.

VSSD – 0.5

–

VDDIO +

0.5

VSIO

DC input voltage on SIO

Output disabled

VSSD – 0.5

–

Output enabled

VSSD – 0.5

–

VIND

Voltage at boost converter input

0.5

–

5.5

VBAT

Boost converter supply

VSSD – 0.5

–

5.5

IVDDIO

Current per VDDIO supply pin

–

100

IGPIO

GPIO current

–30

–

ISIO

SIO current

–49

–

IUSBIO

USBIO current

–56

–

Latch up current[12]

–140

–

140

ESDHBM

Electrostatic discharge voltage

Human body model

2000

–

ESDCDM

ESD voltage

Charge device model

500

–

Notes

11. The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin ≤ VDDIO ≤ VDDA.

12. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.

CY8C54LP датащи(PDF) 62 Page - Cypress Semiconductor

CY8C54LP датащи(HTML) 62 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL