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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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W49V002FAQ датащи(PDF) 7 Page - Winbond |
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W49V002FAQ датащи(HTML) 7 Page - Winbond |
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7 / 32 page  W49V002FA Publication Release Date: February 19, 2002 - 7 - Revision A2 FWH CYCLE DEFINITION FIELD NO. OF CLOCKS DESCRIPTION START 1 "1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH Memory Write cycle. IDSEL 1 This one clock field indicates which FWH component is being selected. MSIZE 1 Memory Size. There is always show “0000b” for single byte access. TAR 2 Turned Around Time ADDR 7 Address Phase for Memory Cycle. FWH supports the 28 bits address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e. Address[27:24] on FWH[3:0] first , and Address[3:0] on FWH[3:0] last.) SYNC N Synchronous to add wait state. "0000b" means Ready, "0101b" means Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error, and other values are reserved. DATA 2 Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first , then DQ[7:4] on FWH[3:0] last.) |
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