RT7263B datasheet(13/15 Pages) RICHTEK

13 / 15 page

RT7263B

DS7263B-01

September 2012

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Thermal Shutdown

Thermal shutdown in implemented to prevent the chip from

operating at excessively high temperatures. When the

junction temperature is higher than 150

°C, the chip is

shut down the switching operation. The chip is

automatically re-enabled when the junction temperature

cools down by approximately 30

°C.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the ambient temperature, and

θJAis the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

θJA, is layout dependent. For

WDFN-14L 4x3 package, the thermal resistance,

θJA, is

°C/W on a standard JEDEC 51-7 four-layer thermal test

board. The maximum power dissipation at TA = 25

°C can

be calculated by the following formula :

PD(MAX) = (125

°C − 25°C) / (60°C/W) = 1.667W for

WDFN-14L 4x3 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curve in Figure 7 allows the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

Figure 7. Derating Curve of Maximum Power Dissipation

0.00

0.30

0.60

0.90

1.20

1.50

1.80

255075

100

125

Ambient Temperature (°C)

Four-Layer PCB

Layout Considerations

Follow the PCB layout guidelines for optimal performance

of the IC.

Keep the traces of the main current paths as short and

wide as possible.

Put the input capacitor as close as possible to the device

pins (VIN and GND).

SW node is with high frequency voltage swing and

should be kept at small area. Keep analog components

away from the SW node to prevent stray capacitive noise

pickup.

Connect feedback network behind the output capacitors.

Keep the loop area small. Place the feedback

components near the IC.

Connect all analog grounds to a common node and then

connect the command node to the power ground behind

the output capacitors.

An example of PCB layout guide is shown in Figure 8

for reference.

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