RT7253A

11

DS7253A-02 March 2011

www.richtek.com

OUT

L

OUT

1

VI

ESR

8fC

⎡⎤

Δ≤ Δ

+

⎢⎥

⎣⎦

The output ripple will be highest at the maximum input

voltage since

capacitors placed in parallel may be needed to meet the

ESR and RMS current handling requirement. Dry tantalum,

special polymer, aluminum electrolytic and ceramic

capacitors are all available in surface mount packages.

Special polymer capacitors offer very low ESR value.

However, it provides lower capacitance density than other

types. Although Tantalum capacitors have the highest

capacitance density, it is important to only use types that

pass the surge test for use in switching power supplies.

Aluminum electrolytic capacitors have significantly higher

ESR. However, it can be used in cost-sensitive applications

for ripple current rating and long term reliability

considerations. Ceramic capacitors have excellent low

ESR characteristics but can have a high voltage coefficient

and audible piezoelectric effects. The high Q of ceramic

capacitors with trace inductance can also lead to significant

ringing.

Higher values, lower cost ceramic capacitors are now

becoming available in smaller case sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. However, care must

be taken when these capacitors are used at input and

output. When a ceramic capacitor is used at the input

and the power is supplied by a wall adapter through long

wires, a load step at the output can induce ringing at the

response as described in a later section.

The output ripple,

and be mistaken as loop instability. At worst, a sudden

inrush of current through the long wires can potentially

part.

Checking Transient Response

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

equal to

overshoot or ringing that would indicate a stability problem.

EMI Consideration

Since parasitic inductance and capacitance effects in PCB

circuitry would cause a spike voltage on SW pin when

high side MOSFET is turned-on/off, this spike voltage on

SW may impact on EMI performance in the system. In

order to enhance EMI performance, there are two methods

to suppress the spike voltage. One way is by placing an

R-C snubber between SW and GND and locking them as

close as possible to the SW pin (see Figure 5). Another

method is by adding a resistor in series with the bootstrap

capability to the high side MOSFET. It is strongly

recommended to reserve the R-C snubber during PCB

layout for EMI improvement. Moreover, reducing the SW

trace area and keeping the main power in a small loop will

be helpful on EMI performance. For detailed PCB layout

guide, please refer to the section Layout Considerations.

Figure 5. Reference Circuit with Snubber and Enable Timing Control

VIN

EN

GND

BOOT

FB

SW

7

5

2

3

1

L

10µH

100nF

22µFx2

R1

75k

R2

24k

3.3V/2A

10µF x 2

Chip Enable

4.5V to 17V

RT7253A

SS

8

0.1µF

COMP

3.3nF

13k

NC

6

4,

9 (Exposed Pad)

* : Optional