Features

PXS20 Product Brief, Rev. 1

Freescale Semiconductor

13

The main features of the SRAMC provide connectivity for the following interfaces:

•

XBAR Slave Port (64-bit data path)

•

ECSM (ECC Error Reporting, error injection and configuration)

•SRAM array

The following functions are implemented:

•

ECC encoding (32-bit boundary for data and complete address bus)

•

ECC decoding (32-bit boundary and entire address)

•

Address translation from the AHB protocol on the XBAR to the SRAM array

The platform SRAM controller is replicated for each processor.

2.5.9

Memory Subsystem Access Time

Every memory access the CPU performs requires at least one system clock cycle for the data phase of the

access. Slower memories or peripherals may require additional data phase wait states. Additional data

phase wait states may also occur if the slave being accessed is not parked on the requesting master in the

crossbar.

2.5.10

Error Correction Status Module (ECSM)

The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash

memory and SRAM). It does not implement the actual ECC calculation. A detected error (double error for

flash memory or SRAM) is also reported to the FCCU. The following errors and indications are reported

into the ECSM dedicated registers:

•

ECC error status and configuration for flash memory and SRAM

•

ECC error reporting for flash memory

Table 2. Platform Memory Access Time Summary

AHB transfer

Data phase

wait states

Description

e200z4d instruction fetch

0

Flash memory prefetch buffer hit (page hit)

e200z4d instruction fetch

3

Flash memory prefetch buffer miss

(based on 4-cycle random flash array access time)

e200z4d data read

0–1

SRAM read

e200z4d data write

0

SRAM 32-bit write

e200z4d data write

0

SRAM 64-bit write (executed as 2 x 32-bit writes)

e200z4d data write

0–2

SRAM 8-,16-bit write

(Read-modify-Write for ECC)

e200z4d flash memory read

0

Flash memory prefetch buffer hit (page hit)

e200z4d flash memory read

3

Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle

of program flash memory controller arbitration)