WM8351CGEBSLASHV datasheet(91/330 Pages) WOLFSON

91 / 330 page

Production Data

WM8351

PD, April 2012, Rev 4.5

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

8:9

AIF_FMT [1:0]

2S)

Data format

00 = Right Justified

01 = Left Justified

10 = I

11 = DSP / PCM mode

Note - see Section 13.11 for the

selection of 8-bit mode.

R114 (72h)

Audio

Interface

ADC

Control

AIFADC_PD

Enables a pull down on ADC data pin

0 = disabled

1 = enabled

AIFADCL_SRC

Selects Left channel ADC output.

0 = ADC Left channel

1 = ADC Right channel

AIFADCR_SRC

Selects Right channel ADC output.

0 = ADC Left channel

1 = ADC Right channel

AIFADC_TDM_

CHAN

ADCDAT TDM Channel Select

0 = ADCDAT outputs data on slot 0

1 = ADCDAT output data on slot 1

AIFADC_TDM

ADC TDM Enable

0 = Normal ADCDAT operation

1 = TDM enabled on ADCDAT

R115 (73h)

Audio

Interface

DAC

Control

AIFDAC_PD

Enables a pull down on DAC data pin

0 = disabled

1 = enabled

DACL_SRC

Selects Left channel DAC input.

0 = DAC Left channel

1 = DAC Right channel

DACR_SRC

Selects Right channel DAC input.

0 = DAC Left channel

1 = DAC Right channel

AIFDAC_TDM_

CHAN

DACDAT TDM Channel Select

0 = DACDAT outputs data on slot 0

1 = DACDAT output data on slot 1

AIFDAC_TDM

DAC TDM Enable

0 = Normal DACDAT operation

1 = TDM enabled on DACDAT

Table 46 Selecting the Audio Data Format

In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 50 Left Justified Audio Interface (assuming n-bit word length)

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