WM8321 datasheet(122/253 Pages) WOLFSON

122 / 253 page

WM8321

Production Data

PD, February 2012, Rev 4.0

122

ADDRESS

BIT

LABEL

DESCRIPTION

IM_HC_INT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_UV_INT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 64 Primary Interrupt Status and Mask Bits

23.2 SECONDARY INTERRUPTS

The following sections define the secondary interrupt status and control bits associated with each of

the primary interrupt bits defined in Table 64.

23.2.1 POWER STATE INTERRUPT

The primary PS_INT interrupt comprises three secondary interrupts as described in Section 11.4. The

secondary interrupt bits are defined in Table 65.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a PS_INT interrupt. The secondary interrupt bits in R16402

(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked

by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16402

(4012h)

Interrupt Status

PS_POR_EINT

Power On Reset interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

PS_SLEEP_OFF_EINT

SLEEP or OFF interrupt (Power state

transition to SLEEP or OFF states)

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

PS_ON_WAKE_EINT

ON or WAKE interrupt (Power state

transition to ON state)

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16410

(401Ah)

Interrupt Status

2 Mask

IM_PS_POR_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_PS_SLEEP_OFF_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_PS_ON_WAKE_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 65 Power State Interrupts

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