WM8321 datasheet(120/253 Pages) WOLFSON

120 / 253 page

WM8321

Production Data

PD, February 2012, Rev 4.0

120

The interrupt logic is illustrated in Figure 24.

event-level register

bit (read only)

e.g. RTC_ALM_EINT

event / fault

condition sets

secondary interrupt

e.g. RTC Alarm

“mask” register bit

(read/write)

e.g. IM_RTC_ALM_EINT

Writing ‘1’ to this bit

clears the

secondary interrupt

AND

other secondary

interrupts

e.g. RTC_PER_EINT

NOR

IRQ pin

other primary interrupts

e.g. WDOG_INT,

AUXADC_INT

AND

“mask” register bit

(read/write)

e.g. IM_RTC_INT

Primary interrupt

(read only)

e.g. RTC_INT

IRQ mask bit

IM_IRQ

Figure 24 Interrupt Logic

Following the assertion of the IRQ

¯¯¯ pin to indicate an Interrupt event, the host processor can determine

which primary interrupt caused the event by reading the primary interrupt register R16400 (4010h).

This register is defined in Section 23.1.

After reading the primary interrupt register, the host processor must read the corresponding

secondary interrupt register(s) in order to determine which specific event caused the IRQ

¯¯¯ pin to be

asserted. The host processor clears the secondary interrupt bit by writing a logic 1 to that bit.

23.1 PRIMARY INTERRUPTS

The primary interrupts are defined in Table 64. These bits are Read Only. They are set when any of

the associated unmasked secondary interrupts is set. They can only be reset when all of the

associated secondary resets are cleared or masked.

Each primary interrupt can be masked. When a mask bit is set, the corresponding primary interrupt is

masked and does not cause the IRQ

¯¯¯ pin to be asserted. The primary interrupt bits in R16408 (4018h)

are valid regardless of whether the mask bit is set. The primary interrupts are all masked by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16400

(4010h)

System

Interrupts

PS_INT

Power State primary interrupt

0 = No interrupt

1 = Interrupt is asserted

TEMP_INT

Thermal primary interrupt

0 = No interrupt

1 = Interrupt is asserted

GP_INT

GPIO primary interrupt

0 = No interrupt

1 = Interrupt is asserted

ON_PIN_INT

ON Pin primary interrupt

0 = No interrupt

1 = Interrupt is asserted

WDOG_INT

Watchdog primary interrupt

0 = No interrupt

1 = Interrupt is asserted

AUXADC_INT

AUXADC primary interrupt

0 = No interrupt

1 = Interrupt is asserted

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