Production Data

WM9082

w

PD, August 2012, Rev 4.1

11

ID

FUNCTION

DESCRIPTION

CONTROL

CODE

Code 1

Start Up (3.6V SPKVDD)

Fast Start-Up for default SPKVDD

AA

Code 2

Standby

Disable Class D output

66

Code 3

EMI control 1

Invert SR[1]

F0

Code 4

32kHz mode control

Select 32kHz sample rate mode

8B

Code 5

High Pass Filter control

Disable 2Hz High Pass Filter

39

Code 6

Page 2 access

Enable Page 2 Control Codes

56

Code 7

Reserved

D1

Code 8

Reserved

D2

Code 9

Start Up (3.6V SPKVDD)

Start-Up for SPKVDD = 3.6V

D4

Code 10

Start Up (5.0V SPKVDD)

Start-Up for SPKVDD = 5.0V

D8

Table 2 WM9082 Page 1 Control Codes

ID

FUNCTION

DESCRIPTION

CONTROL

CODE

Code 1

Reserved

AA

Code 2

Reserved

66

Code 3

Performance control 1

Invert PC1[0]

F0

Code 4

Reserved

8B

Code 5

Reserved

39

Code 6

Reserved

56

Code 7

Reserved

D1

Code 8

Reserved

D2

Code 9

EMI control 2

Invert SR[0]

D4

Code 10

Performance control 2

Increment PC2[1:0]

D8

Table 3 WM9082 Page 2 Control Codes

The output driver slew-rate control is configurable using the SR[1] and SR[0] bits. These fields are

defined in Table 4. The slew-rate Control Code sequences are described in Table 6.

SR[1]

SR[0]

OUTPUT SLEW RATE

(OUTPUT RISE / FALL TIME)

0

0

5ns (Default)

0

1

10ns

1

0

20ns

1

1

40ns

Table 4 Output Slew Rate Control bits

The output driver operating mode is configurable using the PC1[0] and PC2[1:0] bits. These fields are

defined in Table 5. Selected operating mode Control Code sequences are described in Table 6.

PC1[0]

PC2[1:0]

DESCRIPTION

1

00

Best PSRR

1

01

↑

↓

(default)

1

10

↑

↓

1

11

↑

↓

0

XX

Best SNR

Table 5 Operating Mode Control bits