WM8988 datasheet(39/56 Pages) WOLFSON

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WM8988

PD, Rev 4.0, October 2008

CLOCKING AND SAMPLE RATES

The WM8988 supports a wide range of master clock frequencies on the MCLK pin, and can generate

many commonly used audio sample rates directly from the master clock. The ADC and DAC must

always run at the same sample rate.

There are two clocking modes:

•

‘Normal’ mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their multiples

(Note: fs refers to the ADC or DAC sample rate, whichever is faster)

•

USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in

systems with a USB interface, and eliminates the need for an external PLL to generate

another clock frequency for the audio codec.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

CLKDIV2

Master Clock Divide by 2

1 = MCLK is divided by 2

0 = MCLK is not divided

5:1

SR [4:0]

00000

Sample Rate Control

R8 (08h)

Clocking and

Sample Rate

Control

USB

Clocking Mode Select

1 = USB Mode

0 = ‘Normal’ Mode

Table 35 Clocking and Sample Rate Control

The clocking of the WM8988 is controlled using the CLKDIV2, USB, and SR control bits. Setting the

CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.

Each value of SR[4:0] selects one combination of MCLK division ratios and hence one combination

of sample rates (see next page). Since all sample rates are generated by dividing MCLK, their

accuracy depends on the accuracy of MCLK. If MCLK changes, the sample rates change

proportionately.

Note that some sample rates (e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their

target value by a very small amount. This is not audible, as the maximum deviation is only 0.27%

(8.0214kHz instead of 8kHz in USB mode). By comparison, a half-tone step corresponds to a 5.9%

change in pitch.

The SR[4:0] bits must be set to configure the appropriate ADC and DAC sample rates in both master

and slave mode.

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