WM8762

Production Data

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PD, Rev 4.6, November 2011

6

Notes:

1.

Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted

over a 20Hz to 20kHz bandwidth.

2.

All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a

filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical

Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification

values.

3.

Power down occurs 1.5

s after MCLK stops.

TERMINOLOGY

1.

Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no

signal applied. (No Auto-zero or Automute function is employed in achieving these results).

2.

Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a

THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.

THD+N @ -60dB= -32dB, DR= 92dB).

3.

THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

4.

Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).

5.

Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the

other. Normally measured by sending a full scale signal down one channel and measuring the other.

POWER ON RESET (POR)

The WM8762 has an internal power-on-reset (POR) circuit which is used to reset the digital

logic into a default state after power up. A block diagram of the reset circuit is shown in Figure 1.

Figure 1 Block Diagram of Power-On-Reset

The active low reset signal NPOR will be asserted low until VDD=2.4V, which means VMID

rises to 1.2V. When this threshold has been reached, then the NPOR is released and the digital

interface has been reset. This is illustrated in the diagram shown in Figure 2.