LPC810M021FN8 datasheet(29/67 Pages) NXP

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LPC81xM

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Objective data sheet

Rev. 1.0 — 7 November 2012

29 of 67

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Limiting values

[1]

The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

c) The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is not

guaranteed. The conditions for functional operation are specified in Table 9.

[2]

Maximum/minimum voltage above the maximum operating voltage (see Table 9) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3]

Including voltage on outputs in tri-state mode. Does not apply to pin PIO0_6.

[4]

VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.

[5]

VDD present or not present.

[6]

If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below

VDD without affecting the hysteresis range of the comparator function.

[7]

It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol

Parameter

Conditions

Min

Max

Unit

VDD

supply voltage (core and external rail)

[2]

0.5

+4.6

input voltage

5 V tolerant I/O

pins; only valid

when the VDD

supply voltage is

present

[3]

0.5

+5.5

5 V open-drain pins

PIO0_10 and

PIO0_11

[4]

0.5

+5.5

3 V tolerant I/O pin

PIO0_6

[5]

0.5

+3.6

VIA

analog input voltage

[6]

[7]

0.5 V

4.6

Vi(xtal)

crystal input voltage

[2]

0.5

+2.5

IDD

supply current

per supply pin

100

ISS

ground current

per ground pin

100

Ilatch

I/O latch-up current

(0.5V

DD) < VI <

(1.5VDD);

Tj < 125 C

100

Tstg

storage temperature

non-operating

[8]

65

+150

C

Tj(max)

maximum junction temperature

150

C

Ptot(pack)

total power dissipation (per package)

based on package

heat transfer, not

device power

consumption

<tbd>

VESD

electrostatic discharge voltage

human body

model; all pins

[9] -

<tbd>

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