MAX15021 datasheet(14/24 Pages) MAXIM

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Use the following equation to calculate the input ripple

when only one regulator is enabled:

The MAX15021 includes UVLO hysteresis to avoid possi-

ble unintentional chattering during turn-on. Use additional

bulk capacitance if the input source impedance is high. If

using a lower input voltage, additional input capacitance

helps to avoid possible undershoot below the undervolt-

age lockout threshold during transient loading.

Output-Capacitor Selection

The allowed output-voltage ripple and the maximum

deviation of the output voltage during load steps deter-

mine the required output capacitance and its ESR. The

output ripple is mainly composed of

ΔVQ (caused by

the capacitor discharge) and

ΔVESR (caused by the

voltage drop across the equivalent series resistance of

the output capacitor). The equations for calculating the

output capacitance and its ESR are:

where

ΔIP-P is the peak-to-peak inductor current, and

fSW is the switching frequency.

ΔVESR and ΔVQ are not directly additive since they are

out of phase from each other. If using ceramic capaci-

tors, which generally have low ESR,

ΔVQ dominates. If

using electrolytic capacitors,

ΔVESR dominates.

The allowable deviation of the output voltage during

fast load transients also affects the output capacitance,

its ESR, and its equivalent series inductance (ESL). The

output capacitor supplies the load current during a

load step until the controller responds with an

increased duty cycle. The response time (tRESPONSE)

depends on the gain bandwidth of the controller (see

the

Compensation-Design Guidelines section). The

resistive drop across the output capacitor’s ESR

(

ΔVESR), the drop across the capacitor’s ESL (ΔVESL),

and the capacitor discharge (

ΔVQ) cause a voltage

droop during the load-step (ISTEP). Use a combination

of low-ESR tantalum/aluminum electrolyte and ceramic

capacitors for better load transient and voltage ripple

performance. Nonleaded capacitors and capacitors in

parallel help reduce the ESL. Keep the maximum out-

put voltage deviation below the tolerable limits of the

electronics being powered.

Use the following equations to calculate the required

output capacitance, ESR, and ESL for minimal output

deviation during a load step:

where ISTEP is the load step, tSTEP is the rise time of the

load step, and tRESPONSE is the response time of the

controller.

Compensation-Design Guidelines

The MAX15021 uses a fixed-frequency, voltage-mode

control scheme that regulates the output voltage by

comparing the output voltage against a fixed reference.

The subsequent “error” voltage that appears at the

error-amplifier output (COMP_) is compared against an

internal ramp voltage to generate the required duty

cycle of the pulse-width modulator. A second-order

lowpass LC filter removes the switching harmonics and

passes the DC component of the pulse-width-modulat-

ed signal to the output. The LC filter has an attenuation

slope of -40dB/decade and introduces 180° of phase

shift at frequencies above the LC resonant frequency.

This phase shift in addition to the inherent 180° of

phase shift of the regulator’s negative feedback system

turns the feedback into unstable positive feedback. The

error amplifier and its associated circuitry must be

designed to achieve a stable closed-loop system.

The basic controller loop consists of a power modulator

(comprised of the regulator’s pulse-width modulator,

associated circuitry, and LC filter), an output feedback

divider, and an error amplifier. The power modulator has

a DC gain set by VAVIN/VRAMP where the ramp voltage

(VRAMP) is a function of the VAVIN and results in a fixed

DC gain of 4V/V, providing effective feed-forward com-

pensation of input-voltage supply DC variations. The

feed-forward compensation eliminates the dependency

of the power modulator’s gain on the input voltage such

that the feedback compensation of the error amplifier

requires no modifications for nominal input-voltage

changes. The output filter is effectively modeled as a

double-pole and a single zero set by the output induc-

tance (L), the DC resistance of the inductor (DCR), the

output capacitance (COUT) and its equivalent series

resistance (ESR).

ESR m

[mV]

[A]

[A] t

V [V]

ESL

[mV] t

[A]

ESR

STEP

OUT

STEP

RESPONSE

ESL

STEP

[]

[A]

V [V] f

[MHz]

ESR m

[mV]

[A]

OUT

QSW

ESR

[]

μ=

××

−

[A]

[V]

CIN(RMS)

LOAD(MAX)

OUT_

PVIN_

OUT_

PVIN_

=×

×−

()

Dual, 4A/2A, 4MHz, Step-Down DC-DC

Regulator with Tracking/Sequencing Capability

MAX15021

Maxim Integrated

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