M95320-DR datasheet(25/48 Pages) STMICROELECTRONICS

номер детали	M95320-DR

подробное описание детали	32-Kbit serial SPI bus EEPROM with high-speed clock

PDF	48 Pages

Scroll/Zoom	100%

производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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M95320-W M95320-R M95320-DR

Instructions

Doc ID 5711 Rev 14

25/48

6.6.1

Cycling with Error Correction Code (ECC)

M95320-D devices offer an Error Correction Code (ECC) logic. The ECC is an internal logic

function which is transparent for the SPI communication protocol.

The ECC logic is implemented on each group of four EEPROM bytes(c). Inside a group, if a

single bit out of the four bytes happens to be erroneous during a Read operation, the ECC

detects this bit and replaces it with the correct value. The read reliability is therefore much

improved.

Even if the ECC function is performed on groups of four bytes, a single byte can be

written/cycled independently. In this case, the ECC function also writes/cycles the three

other bytes located in the same group(c). As a consequence, the maximum cycling budget is

defined at group level and the cycling can be distributed over the four bytes of the group: the

sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain

below the maximum value defined in Table 13.

A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.

M95320-DR датащи(PDF) 25 Page - STMicroelectronics