AD9558 datasheet(89/104 Pages) AD

89 / 104 page

Data Sheet

AD9558

Rev. A | Page 89 of 104

REFB Profile (Register 0x0740 to Register 0x0766)

REFB Profile Register 0x0740 to Register 0x0766 are identical to REFA Profile Register 0x0700 to Register 0x0726.

REFC Profile (Register 0x0780 to Register 0x07A6)

REFC Profile Register 0x0780 to Register 0x07A6 are identical to REFA Profile Register 0x0700 Register 0x0726.

REFD Profile (Register 0x07C0 to Register 0x07E6)

REFD Profile Register 0x07C0 to Register 0x07E6 are identical to REFA Profile Register 0x0700 to Register 0x0726.

OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A10)

Table 89. General Power-Down

Address

Bits

Bit Name

Description

Soft reset exclude regmap

Resets device but retains programmed register values (default: not reset)

DCO power-down

Places DCO in deep sleep mode (default: not powered down)

SYSCLK power-down

Places SYSCLK input and PLL in deep sleep mode (default: not powered down)

Reference input power-down

Places reference clock inputs in deep sleep mode (default: not powered down)

TDC power-down

Places the time-to-digital converter in deep sleep mode (default: not powered down)

APLL power-down

Places the output PLL in deep sleep mode (default: not powered down)

Clock dist power-down

Places the clock distribution outputs in deep sleep mode (default: not powered down)

0x0A00

Full power-down

Places the entire device in deep sleep mode (default: not powered down)

Table 90. Loop Mode

Address

Bits

Bit Name

Description

0x0A01

Reserved

Reserved.

User holdover

Forces the device into holdover mode (default: not forced holdover mode).

If a tuning word history is available, then the history tuning word specifies the DCO

output frequency. Otherwise, the free run frequency tuning word register specifies the

DCO output frequency.

The phase and frequency lock detectors are forced into the unlocked state.

User freerun

Forces the device into user free run mode (default is not forced user free run mode).

The free run frequency tuning word register specifies the DCO output frequency. When

the user freerun bit is set, it overrides the user holdover bit (Address 0x0A01, Bit 6).

[4:2]

REF switchover mode

Selects the operating mode of the reference switching state machine.

Reference Switchover Mode, Bits[2:0]

Reference Selection Mode

000 (default)

001

010

011

100

101

110

111

Automatic revertive mode

Automatic nonrevertive mode

Manual reference select

(with automatic fallback mode)

Manual reference select mode

(with auto-holdover)

Full manual mode (no auto-holdover)

Not used

[1:0]

User reference in manual

switchover mode

Input reference when REF switchover mode bits (Register 0x0A01, Bits[4:2]) = 010, 011, or 100.

00 (default) = Input Reference A.

01 = Input Reference B.

10 = Input Reference C.

11 = Input Reference D.

Table 91. Cal/Sync Distribution

Address

Bits

Bit Name

Description

[7:2]

Reserved

Default: 0x00

Soft sync clock distribution

Setting this bit initiates synchronization of the clock distribution output (default: 0b).

Nonmasked outputs stall when value is 1b; restart is initialized on 1b to 0b transition.

0x0A02

Reserved

Default: 0b.

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