SPEAR1340 datasheet(176/200 Pages) STMICROELECTRONICS

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Timing characteristics

SPEAr1340

176/200

Doc ID 023063 Rev 4

The timings have been calculated in best and worst case, without considering the pads

contribution. These are the operating conditions used for the characterization:

●

In worst case: V=1.10 V, T=125 ° C

●

In best case: V=1.30 V, T= -40 ° C

ADDR/CTRL timing characteristics

The memory clock (mem_clk) is derived from a fixed dedicated PLL output. Address and

control signals (mem_ctl) are launched on the negative edge of the mem_clk

(+/- 1/8 * Tmem_clk) in order to have the control signals centered on the rising edge of the

clock at memory side (assuming the same board flight-time delay for mem_clk and

mem_ctl).

The address and control signals have the same output stage, but they present a skew of

about 114 ps due to the physical implementation.

For a frequency of 533.3 MHz, the period of the clock is TCLK = 1.875 ns.

The setup time is calculated considering:

●

maximum error = 235 ps

●

maximum data skew = 114 ps

Ts calculation formula

Ts= Tclk/2–data_skew –max_error= 938 ps – 114 ps – 235 ps= 589 ps

The hold time, instead, is calculated considering:

●

maximum error = 0 ps

●

maximum data skew = 114 ps

Th calculation formula

Th= Tclk/2–data_skew + max_error= 938 ps – 114 ps + 0 ps= 824 ps

Table 90.

ADDR/CTRL timing characteristics

Symbol

Description

Value

Unit

TCLK

Mem_clk period

1.875

Setup time for ADDR/CTRL receive data

589

Hold time for ADDR/CTRL receive data

824

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