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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPEAR1340 датащи(PDF) 174 Page - STMicroelectronics |
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SPEAR1340 датащи(HTML) 174 Page - STMicroelectronics |
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174 / 200 page  Timing characteristics SPEAr1340 174/200 Doc ID 023063 Rev 4 5.11.2 CompactFlash true IDE PIO mode/UDMA mode This section describes the timing characteristics for MCIF when interfacing CompactFlash in true IDE mode PIO mode and UDMA mode. The data in Table 88 has been measured in the following configuration: – True IDE PIO mode = Mode 6 – HCLK period = 6 ns – CF/XD (clk_xin) base clock period obtained by programming the MISC register MCIF_CFXD_CLK_SYNT. –Tclk_xin = T – t0 is the minimum total cycle time. t0 must satisfy the following constraint t0 ≥ t2 + t2i t2 is the minimum command active time. t2i is the minimum command active recovery time or command inactive time. Figure 35. MCIF - CF true IDE PIO mode waveform Table 88. MCIF - CF true IDE PIO mode timing characteristics Symbol Description Min Max Unit t0 Cycle time 18*T ns t1 Address Valid to IORD/IOWR setup 2*T ns t2 IORD/-IOWR 10*T ns t2i IORD/-IOWR recovery time 8*T ns t3 IOWR data setup 9.5*T ns t4 IOWR data hold T - 3.2 ns t5 IORD data setup 5(1) 1. t5 and t6 are the minimum timing requirements the external card has to respect in order to ensure correct Read Data sampling inside SPEAr1340. ns t6 IORD data hold 4(1) ns t0 t4 t3 DATAOUT DATAIN t2 t5 t6 t1 t2 i MCIF_Addr2, MCIF_Addr1_CLE_CLK MCIF_Addr0_ALE MCIF_nCS0_nCE MCIF_nCS1 MCIF_nIOWR_nWE MCIF_nIORD_nRE MCIF_Data[15:0] MCIF_Data[15:0] |
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