 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
SPEAR1340 датащи(PDF) 168 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
SPEAR1340 датащи(HTML) 168 Page - STMicroelectronics |
|
|
168 / 200 page  Timing characteristics SPEAr1340 168/200 Doc ID 023063 Rev 4 5.8 GPIO/XGPIO timing characteristics For edge-sensitive signals, the interrupt line is sampled by flip flops clocked by PCLK for GPIOs and HCLK for XGPIOs, the APB and AHB clocks, normally running at 83 MHz and 166 MHz respectively. The minimum pulse width required for interrupt detection on signal edge is: 3*TPCLK (36 ns at 83 MHz) for GPIO 3*THCLK (18 ns at 166 MHz) for XGPIO 5.9 I2C timing characteristics The timing of high and low level of SCL (TSCLHigh and TSCLLow) are programmable. Figure 31. I2C timing waveform TCLKlow MAC_MDC pulse width low 60 ns Ts Setup time for MDIO input 30 ns Th Hold time for MDIO input 0 ns 1. When MDIO is used as output, the data is launched on the falling edge of the clock as shown in Figure 30. Table 78. MAC_MDC/MAC_MDIO timing characteristics (continued) Symbol Description Min Max Unit I2Cx_SCL I2Cx_SDA tSCLHigh tSU-STA tHD-STA tSU-DAT tSU-STO tHD-STO tSCLLow |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
