SPEAR1340 datasheet(107/200 Pages) STMICROELECTRONICS

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SPEAr1340

Pin description

Doc ID 023063 Rev 4

107/200

MAC_RXCLK

Reception clock (rmii_clk)

This is the reception clock (125/25/2.5 MHz in 1G/100M/10Mbps) provided

by the external PHY for RGMII,GMII,MII. All the RGMII,GMII,MII receive

signals received by the MAC are synchronous to this clock.

IP28

MAC_RXDV

PHY receive data valid

This signal is driven by PHY and has multiple functions depending on

which PHY interface is selected as given below.

– GMII/MII: When high, indicates that data on the MAC_RXD bus is valid.

It remains asserted continuously from the first recovered byte/nibble of

the frame through the final recovered byte/nibble.

– RGMII: This is the receive control signal used to qualify the data

received on MAC_RXD bus. This signal is sampled on both edges of the

clock.

– RMII: Contains the crs and data valid information of the receive

interface.

IM27

MAC_RXER

PHY receive error

This signal is driven by the PHY and has multiple functions depending on

which PHY interface is selected as given below.

– GMII/MII: When high, indicates an error or carrier extension (in GMII) in

the received frame on the MAC_RXD bus.

– RGMII/RMII: Not used.

IM28

MAC_RXD0

PHY receive data

This is a bundle of eight data signals received from the PHY. It has multiple

functions depending on which PHY interface is selected, as given below.

– GMII: All 8 bits provide the GMII receive data byte. The validity of the

data is qualified with MAC_RXDV and MAC_RXER.

Note: Using 10/100 Mbps-only operation, MAC_RXD bus is only 4 bits

wide (MAC_RXD[3:0]).

– MII: Bits [3:0] provide the MII receive data nibble. The validity of the data

is qualified with MAC_RXDV and MAC_RXER.

– RGMII: Bits [3:0] provide the RGMII receive data. The data bus is

sampled with both rising and falling edges of the receive clock

(MAC_RXCLK). The validity of the data is qualified with MAC_RXDV.

– RMII: Bits [1:0] provide the RMII receive data. The validity of the data is

qualified with MAC_RXDV.

R27

MAC_RXD1

R24

MAC_RXD2

P25

MAC_RXD3

N24

MAC_RXD4

N25

MAC_RXD5

N26

MAC_RXD6

M24

MAC_RXD7

M25

MAC_COL

PHY collision

This signal, valid only in GMII/MII mode, is asserted by the PHY when a

collision is detected on the medium. This signal is not synchronous to any

clock.(Active high)

IM26

MAC_CRS

PHY CRS

This signal, valid only in GMII/MII mode, is asserted by the PHY when

either the transmit or receive medium is not idle. The PHY deasserts this

signal when both transmit and receive medium are idle. This signal is not

synchronous to any clock. (active high)

L26

Table 15.

Connectivity - MAC PHY interface signals description (continued)

Signal name

Description

Type

Ball

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