ST10F280_12 datasheet(33/239 Pages) STMICROELECTRONICS

33 / 239 page

ST10F280

Internal Flash memory

Doc ID 8673 Rev. 3

33/239

5.2.3

Status register

This register is used to flag the status of the memory and the result of an operation. This

operation.

5.2.4

Erase operation

This Flash memory features a block erase architecture with a chip erase capability too.

Erase is accomplished by executing the six cycle erase command sequence. Additional

command write cycles can then be performed to erase more than one block in parallel.

When a time-out period elaps (96

μs) after the last cycle, the Erase-Program Controller

(EPC) automatically starts and times the erase pulse and executes the erase operation.

There is no need to program the block to be erased with ‘0000h’ before an erase operation.

Termination of operation is indicated in the Flash status register. After erase operation, the

Flash memory locations are read as 'FFFFh’ value.

5.2.5

Erase suspend

A block erase operation is typically executed within 1.5 second for a 64K Byte block. Erasure

of a memory block may be suspended, in order to read data from another block or to

program data in another block, and then resumed.

5.2.6

In-system programming

In-system programming is fully supported. No special programming voltage is required.

Because of the automatic execution of erase and programming algorithms, write operations

are reduced to transferring commands and data to the Flash and reading the status. Any

code that programs or erases Flash memory locations (that writes data to the Flash) must

be executed from memory outside the on-chip Flash memory itself (on-chip RAM or external

memory).

A boot mechanism is provided to support in-system programming. It works using serial link

via USART interface and a PC compatible or other programming host.

5.2.7

Read/write protection

The Flash module supports read and write protection in a very comfortable and advanced

protection functionality. If Read Protection is installed, the whole Flash memory is protected

against any "external" read access; read accesses are only possible with instructions

fetched directly from program Flash memory. For update of the Flash memory a temporary

disable of Flash Read Protection is supported.

The device also features a block write protection. Software locking of selectable memory

blocks is provided to protect code and data. This feature will disable both program and erase

operations in the selected block(s) of the memory. Block Protection is accomplished by block

specific lock-bit which are programmed by executing a four cycle command sequence. The

locked state of blocks is indicated by specific flags in the according block status registers. A

block may only be temporarily unlocked for update (write) operations.

With the two possibilities for write protection whole memory or block specific a flexible

installation of write protection is supported to protect the Flash memory or parts of it from

unauthorized programming or erase accesses and to provide virus-proof protection for all

system code blocks. All write protection also is enabled during boot operation.

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