ST10F280_12 datasheet(102/239 Pages) STMICROELECTRONICS

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Parallel ports

ST10F280

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Doc ID 8673 Rev. 3

12.2.1

Alternate functions of Port 0

When an external bus is enabled, PORT0 is used as data bus or address/data bus.

Note that an external 8-bit de-multiplexed bus only uses P0L, while P0H is free for I/O

(provided that no other bus mode is enabled).

PORT0 is also used to select the system start-up configuration. During reset, PORT0 is

configured to input, and each line is held high through an internal pull-up device. Each line

can now be individually pulled to a low level (see DC-level specifications) through an

external pull-down device. A default configuration is selected when the respective PORT0

lines are at a high level. Through pulling individual lines to a low level, this default can be

changed according to the needs of the applications.

The internal pull-up devices are designed such that an external pull-down resistors can be

used to apply a correct low level. These external pull-down resistors can remain connected

to the PORT0 pins also during normal operation, however, care has to be taken such that

they do not disturb the normal function of PORT0 (this might be the case, for example, if the

external resistor is too strong). With the end of reset, the selected bus configuration will be

written to the BUSCON0 register. The configuration of the high byte of PORT0, will be

copied into the special register RP0H. This read-only register holds the selection for the

number of chip selects and segment addresses. Software can read this register in order to

react according to the selected configuration, if required. When the reset is terminated, the

internal pull-up devices are switched off, and PORT0 will be switched to the appropriate

operating mode.

During external accesses in multiplexed bus modes PORT0 first outputs the 16-bit intra-

segment address as an alternate output function. PORT0 is then switched to high-

impedance input mode to read the incoming instruction or data. In 8-bit data bus mode, two

memory cycles are required for word accesses, the first for the low byte and the second for

the high byte of the word. During write cycles PORT0 outputs the data byte or word after

outputting the address. During external accesses in de-multiplexed bus modes PORT0

reads the incoming instruction or data word or outputs the data byte or word.

Figure 29.

Port 0 I/O and alternate functions

When an external bus mode is enabled, the direction of the port pin and the loading of data

into the port output latch are controlled by the bus controller hardware.

The input of the port output latch is disconnected from the internal bus and is switched to the

line labeled “Alternate Data Output” via a multiplexer. The alternate data can be the 16-bit

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