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SPC56XL60/54 датащи(PDF) 6 Page - STMicroelectronics

номер детали SPC56XL60/54
подробное описание детали  32-bit Power Architecture® microcontroller for automotive SIL3/ASILD chassis and safety applications
PDF  160 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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SPC56XL60/54 датащи(HTML) 6 Page - STMicroelectronics

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List of figures
SPC56XL60/54
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Doc ID 15457 Rev 8
List of figures
Figure 1.
SPC56XL60/54 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2.
LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 3.
SPC56XL60/54 LQFP144 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 4.
SPC56XL60/54 LFBGA257 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 5.
BCP68 board schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 6.
Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 7.
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 8.
ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 9.
Input Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 10.
Transient Behavior during Sampling Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 11.
Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 12.
Pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 13.
Destructive Reset Sequence, BIST enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 14.
Destructive Reset Sequence, BIST disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 15.
External Reset Sequence Long, BIST enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 16.
Functional Reset Sequence Long. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 17.
Functional Reset Sequence Short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 18.
Reset sequence start for Destructive Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 19.
Reset sequence start via RESET assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 20.
Reset sequence - External watchdog trigger window position . . . . . . . . . . . . . . . . . . . . . 129
Figure 21.
Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 22.
Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 23.
JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 24.
JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 25.
JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 26.
Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 27.
Nexus EVTI Input Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 28.
Nexus Double Data Rate (DDR) Mode output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 29.
Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 30.
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 31.
DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 32.
DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 33.
DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 34.
DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 35.
DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 36.
DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 37.
DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 38.
DSPI modified transfer format timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 39.
DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 40.
LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 41.
LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 42.
LFBGA257 package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 43.
Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149



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