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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA382BW датащи(PDF) 154 Page - STMicroelectronics |
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STA382BW датащи(HTML) 154 Page - STMicroelectronics |
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154 / 172 page  Register description: Sound Terminal compatibility STA382BW 154/172 Doc ID 022783 Rev 1 Figure 43. Alternate function for INTLINE pin 7.22.5 Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4, D3, D2) As per Section 7.22.2, the assertion of PWDN activates a counter that, by default, after 13 million clock cycles puts the power bridge in tristate mode, independently from the fade-out time. Using these registers it is possible to program this counter according to the following table. Table 173. PNDLSL bits configuration 7.22.6 Short-circuit check enable bit (address 0x4C, bit D0) This bit, when enabled, will activate the short-circuit checks before any power bridge activation (EAPD bit 0->1). See Section 7.20 for more details. Y N ‘0 ’ LPD “is th e device in powerdown?” 0 1 LP D P 0 1 LPD E Po w er B rid ge Fau lt IN T L IN E PNDLSL[2] PNDLSL[1] PNDLSL[2] Fade-out time 00 0 Default time (13M PLL clock cycles) 00 1 Default time divided by 2 01 0 Default time divided by 4 01 1 Default time divided by 8 10 0 Default time divided by 16 10 1 Default time divided by 32 11 0 Default time divided by 64 11 1 Default time divided by 128 |
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