STA381BW datasheet(40/171 Pages) STMICROELECTRONICS

40 / 171 page

I2C bus specification

STA381BW

40/171

Doc ID 018835 Rev 7

the 9th bit time. The byte following the device identification byte is the internal space

address.

5.3

Write operation

Following the START condition, the master sends a device select code with the RW bit set

to 0. The STA381BW acknowledges this and then waits for the byte of the internal address.

After receiving the internal byte address the STA381BW again responds with an

acknowledgement.

5.3.1

Byte write

In the byte write mode the master sends one data byte which is acknowledged by the

STA381BW. The master then terminates the transfer by generating a STOP condition.

5.3.2

Multi-byte write

The multi-byte write mode can start from any internal address. The master generating a

STOP condition terminates the transfer.

5.4

Read operation

5.4.1

Current address byte read

Following the START condition, the master sends a device select code with the RW bit set

to 1. The STA381BW acknowledges this and then responds by sending one byte of data.

The master then terminates the transfer by generating a STOP condition.

5.4.2

Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are

read from sequential addresses within the STA381BW. The master acknowledges each

data byte read and then generates a STOP condition, terminating the transfer.

5.4.3

Random address byte read

Following the START condition, the master sends a device select code with the RW bit set

to 0. The STA381BW acknowledges this and then the master writes the internal address

byte. After receiving the internal byte address, the STA381BW again responds with an

acknowledgement. The master then initiates another START condition and sends the device

select code with the RW bit set to 1. The STA381BW acknowledges this and then responds

by sending one byte of data. The master then terminates the transfer by generating a STOP

condition.

5.4.4

Random address multi-byte read

The multi-byte read mode can start from any internal address. Sequential data bytes are

read from sequential addresses within the STA381BW. The master acknowledges each

data byte read and then generates a STOP condition, terminating the transfer.

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