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STA369BW датащи(PDF) 33 Page - STMicroelectronics

номер детали STA369BW
подробное описание детали  Sound Terminal® 2.1-channel high-efficiency digital audio system
PDF  88 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STA369BW датащи(HTML) 33 Page - STMicroelectronics

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STA369BW
Register description
Doc ID 022033 Rev 1
33/88
7.1
Configuration register A (addr 0x00)
7.1.1
Master clock select
The STA369BW supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input
sampling frequency (fs).
The relationship between the input clock and the input sampling rate is determined by both
the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor
generating the internal clock and the IR bit determines the oversampling ratio used
internally.
D7
D6
D5
D4
D3
D2
D1
D0
FDRB
TWAB
TWRB
IR1
IR0
MCS2
MCS1
MCS0
01
10
00
1
1
Table 9.
Master clock select
Bit
R/W
RST
Name
Description
0R/W
1
MCS0
Selects the ratio between the input I2S sampling
frequency and the input clock
1R/W
1
MCS1
2R/W
0
MCS2
Table 10.
Input sampling rates
Input sampling rate
fs (kHz)
IR
MCS[2:0]
101
100
011
010
001
000
32, 44.1, 48
00
576 * fs
128 * fs
256 * fs
384 * fs
512 * fs
768 * fs
88.2, 96
01
NA
64 * fs
128 * fs
192 * fs
256 * fs
384 * fs
176.4, 192
1X
NA
32 * fs
64 * fs
96 * fs
128 * fs
192 * fs



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