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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA339BWS датащи(PDF) 41 Page - STMicroelectronics |
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STA339BWS датащи(HTML) 41 Page - STMicroelectronics |
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41 / 76 page  STA339BWS Register description Doc ID 15276 Rev 5 41/76 Invalid input detect mute enable Setting the IDE bit enables this function, which looks at the input I2S data and automatically mutes if the signals are perceived as invalid. Binary output mode clock loss detection Detects loss of input MCLK in binary mode and will output 50% duty cycle. LRCK double trigger protection LDTE, when enabled, prevents double trigger of LRCLK on instable I2S input. Auto EAPD on clock loss When active, issues a power device power down signal (EAPD) on clock loss detection. IC power down Table 44. Invalid input detect mute enable Bit R/W RST Name Description 2R/W 1 IDE 0: disables the automatic invalid input detect mute 1: enables the automatic invalid input detect mute Table 45. Binary output mode clock loss detection Bit R/W RST Name Description 3R/W 1 BCLE 0: binary output mode clock loss detection disabled 1: binary output mode clock loss detection enable Table 46. LRCK double trigger protection Bit R/W RST Name Description 4R/W 1 LDTE 0: LRCLK double trigger protection disabled 1: LRCLK double trigger protection enabled Table 47. Auto EAPD on clock loss Bit R/W RST Name Description 5R/W 0 ECLE 0: auto EAPD on clock loss not enabled 1: auto EAPD on clock loss Table 48. IC power down Bit R/W RST Name Description 6R/W 1 PWDN 0: IC power down low-power condition 1: IC normal operation |
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