STA333BW datasheet(27/67 Pages) STMICROELECTRONICS

27 / 67 page

STA333BW

Doc ID 13773 Rev 3

27/67

To make the STA333BW work properly, the serial audio interface LRCKI clock must be

synchronous to the PLL output clock. It means that:

N-4< = (frequency of PLL clock) / (frequency of LRCKI) = < N+4 cycles,

where N depends on the settings in Table 12 on page 23

the PLL must be locked.

If these two conditions are not met, and IDE bit (register 0x05, bit 2) is set to 1, the

STA333BW immediately mutes the I2S PCM data out (provided to the processing block) and

it freezes any active processing task.

Clock desynchronization can happen during STA333BW operation because of source

switching or TV channel change. To avoid audio side effects, like click or pop noise, it is

strongly recommended to complete the following actions:

soft volume change

I2C read / write instructions

while the serial audio interface and the internal PLL are still synchronous.

Delay serial clock enable

Channel input mapping

Each channel received via I2S can be mapped to any internal processing channel via the

Channel Input Mapping registers. This allows for flexibility in processing. The default

settings of these registers maps each I2S input channel to its corresponding processing

channel.

6.1.3

Configuration register C (addr 0x02)

FFX power output mode

The FFX power output mode selects how the FFX output timing is configured.

Table 20.

Delay serial clock enable

Bit

R/W

RST

Name

Description

R/W

DSCKE

0: no serial clock delay

1: serial clock delay by 1 core clock cycle to tolerate

anomalies in some I2S master devices

Table 21.

Channel input mapping

Bit

R/W

RST

Name

Description

6R/W

C1IM

0: processing channel 1 receives left I2S Input

1: processing channel 1 receives right I2S Input

7R/W

C2IM

0: processing channel 2 receives left I2S Input

1: processing channel 2 receives right I2S Input

OCRB

Reserved

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

011

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