STPMC1 datasheet(60/77 Pages) STMICROELECTRONICS

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Theory of operation

STPMC1

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Doc ID 15728 Rev 6

to boost the VCC supply voltage of the STPMC1 to generate the VOTP voltage (14 V to 20

V) needed to program the OTP antifuse elements.

WE (write Enable): This mode signal is used to permanently write to the OTP antifuse

element. When this bit is not set, any write to the configuration bit is recorded in the shadow

latches. When this bit is set the writing is recorded both in the shadow latch and in the OTP

antifuse element.

Precharge: this command increments the index register while reading. After reading a 32-

bit data record it is possible to access next group data records by sending this command.

This way, a faster access to later groups is possible.

TSG0: In standalone mode it is possible to produce a data latching request by a pulse on

test signal TSG0. In fact in such configuration is not possible to latch internal data into

transmission latches because the SYN is an output pin as long as SCS is in idle state and it

is under control of an indicator signal of negative power.

After TSTD configuration bit is set, only the precharge and TSGx commands can be

executed.

9.21

SPI interface (configuration bit SCLP)

The SPI interface supports a simple serial protocol, which is implemented in order to enable

a communication between some master system (microcontroller or PC) and the device.

Three tasks can be performed with this interface:

●

remotely resetting the device,

●

reading data records,

●

writing the mode bits and the configuration bits (temporarily or permanently);

Four pins of the device are dedicated to this purpose: SCS, SYN, SCLNCN, SDATD. SCS,

SYN and SCLNLC are all input pins while SDATD can be input or output according if the

SPI is in write or read mode. A high level signal for these pins means a voltage level higher

than 0.75 x VCC, while a low level signal means a voltage value lower than 0.25 x VCC.

The STPMC1 internal registers are not directly accessible, rather a 32-bit of transmission

latches are used to pre-load the data before being read or written to the internal registers.

The condition in which SCS, SYN and SCLNLC inputs are set to high level determines the

idle state of the SPI interface and no data transfer occurs.

As previously described in the document, when the STPMC1 is in standalone mode, SYN,

SCLNLC and SDATD can provide information on the meter status (see programmable pin

functions) and are not used for SPI communication. In this section, the SYN, SCLNLC and

SDATD operation as part of the SPI interface is described.

SCS: when low, SCS pin enables SPI communication, both in standalone and in peripheral

operating mode. This means that the master can abort any task in any phase by

deactivation of SCS. In standalone mode SCS high enables SYN, SCLNLC and SDATD to

output meter status.

SYN: this pin operates different functions according to the status of SCS pin. When SCS is

low the SYN pin status select if the SPI is in read (SYN = 1) or write mode (SYN = 0). When

SCS is high and SYN is also high the results of the input or output data are transferred to

the transmission latches.

SCLNLC: it is basically the clock pin of the SPI interface. Configuration bit SCLP controls

the polarity of the clock (see configuration bits map). This pin function is also controlled by

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