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LT3029

3029fa

PIN FUNCTIONS

BYP1/BYP2 (Pin 1/Pin 8): Bypass. Use the BYP1/BYP2

pins to bypass the reference of the LT3029 regulator and

achieve low output noise performance. Internal circuitry

clamps the BYP1/BYP2 pins to ±0.6V (one VBE) from

ground. A small capacitor from the corresponding output

to this pin bypasses the reference to lower the output

voltage noise. Using a maximum value of 10nF reduces

the output voltage noise to a typical 20μVRMS over a 10Hz

to 100kHz bandwidth. If not used, this pin must be left

unconnected.

NC (Pin 2): No Connect. This pin is not connected to

any internal circuitry. It may be ﬂoated, tied to VIN or tied

to GND.

OUT1/OUT2 (Pins 3, 4/Pins 6, 7): Output. The outputs

supply power to the loads. A minimum 3.3μF output ca-

pacitor prevents oscillations on each output. Applications

with large output load transients require larger values of

output capacitance to limit peak voltage transients. See

the Applications Information section for more on output

capacitance and reverse output characteristics.

GND (Pin 5, 17): Ground. The exposed pad (Pin 17) of

the DFN and MSOP packages is an electrical connection

to GND. To ensure proper electrical and thermal perfor-

mance, solder Pin 17 to the PCB ground and tie directly

to Pin 5. Connect the bottom of the output voltage setting

resistor divider directly to GND (Pin 5) for optimum load

regulation performance.

IN1/IN2 (Pins 13, 14/Pins 11, 12): Inputs. The IN1/IN2

pins supply power to each channel. The LT3029 requires

a bypass capacitor at the IN1/IN2 pins if located more

than six inches away from the main input ﬁlter capacitor.

Include a bypass capacitor in battery-powered circuits,

as a battery’s output impedance rises with frequency. A

bypass capacitor in the range of 1μF to 10μF sufﬁces. The

LT3029’s design withstands reverse voltages on the IN pins

with respect to ground and the OUT pins. In the case of

a reversed input, which occurs if a battery is plugged in

backwards, the LT3029 acts as if a diode is in series with

its input. No reverse current ﬂows into the LT3029 and no

reverse voltage appears at the load. The device protects

itself and the load.

SHDN1/SHDN2 (Pin 15/Pin 10): Shutdown. Pulling the

SHDN1 or SHDN2 pin low puts its corresponding LT3029

channel into a low power state and turns its output off. The

SHDN1 and SHDN2 pins are completely independent of

each other, and each SHDN pin only affects operation on

its corresponding channel. Drive the SHDN1 and SHDN2

pins with either logic or an open collector/drain with pull-up

resistors. The resistors supply the pull-up current to the

open collectors/drains and the SHDN1 or SHDN2 current,

typically less than 1μA. If unused, connect the SHDN1 and

SHDN2 to their corresponding IN pins. Each channel will

be in its low power shutdown state if its corresponding

SHDN pin is not connected.

ADJ1/ADJ2: (Pin 16/Pin 9) Adjust Pin. These are the error

ampliﬁer inputs. These pins are internally clamped to ±9V.

A typical input bias current of 30nA ﬂows into the pins

(see curve of ADJ1/ADJ2 Pin Bias Current vs Temperature

in the Typical Performance Characteristics section). The

ADJ1 and ADJ2 pin voltage is 1.215V referenced to ground

and the output voltage range is 1.215V to 19.5V.

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