ATSHA204 datasheet(21/65 Pages) ATMEL

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Atmel ATSHA204 [DATASHEET]

8740D

−CRYPTO−3/12

2C Interface

The I

2C interface uses the SDA and SCL pins to indicate various I/O states to the ATSHA204. This interface is designed to be

compatible at the protocol level with the AT24C16B Serial EEPROM operating at 1MHz.

The SDA pin is normally pulled high with an external pull-up resistor, as the ATSHA204 includes only an open-drain driver on

its output pin. The bus master may be either open–drain or totem pole, and if the latter, then it should be tri-stated when the

ATSHA204 is driving results on the bus. The SCL pin is an input, and must be driven both high and low at all times by an

external device

6.1

I/O Conditions

The device responds to the following I/O conditions:

6.1.1

Device is Asleep

When the device is asleep, it ignores all but the wake condition

Wake:

If SDA is held low for a period greater than tWLO, the device exits low-power mode and, after a delay of tWHI,

is ready to receive I

2C commands. The device ignores any levels or transitions on the SCL pin when the

device is idle or asleep and during tWLO. At some point during tWHI, the SCL pin is enabled and the conditions

listed in Section 6.1.2, “Device is Awake,” are honored.

The wake condition requires either that the system processor manually drive the SDA pin low for tWLO, or that a data byte of

0x00 is transmitted at a clock rate sufficiently slow that SDA is low for a minimum period of tWLO. When the device is awake,

the normal processor I

2C hardware and/or software can be used for device communications up to and including the I/O

sequence required toput the device back into low power (sleep) mode.

When there are multiple ATSHA204 devices on the bus and the I

2C interface is run at 133KHz or slower, the transmission of

certain data patterns (such as 0x00) will cause all the ATSHA204 devices on the bus to wake up. Because subsequent device

addresses transmitted along the bus will only match the desired devices, the unused devices will remain idle and not cause

any bus conflicts.

In I

2C mode, the device will ignore a wake sequence sent when the device is already awake.

6.1.2

Device is Awake

When the device is awake, it honors the conditions listed below.

Data Zero:

If SDA is low and stable while SCL goes from low to high to low, then a zero bit is being transferred on the

bus. SDA can change while SCL is low.

Data One:

If SDA is high and stable while SCL goes from low to high to low, then a one bit is being transferred on the

bus. SDA can change while SCL is low.

Figure 6-1.

Data Bit Transfer on I

2C Interface

SDA

SCL

Data line stable;

Data valid

Change of

data allowed

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