– 7 –

CXA2610N

Timing Chart

LD0

ENABLE

CONTR

CONT2

CONT3

OSCENA

Application Circuit

TTL/CMOS

LD

TTL/CMOS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Vcc

Vcc

LD0

GND

OSCGA

ENABLE

OSCENA

Vcc

IINR

IIN2

GND

OSCFR

IIN3

CONTR

CONT2

CONT3

TTL/CMOS

TTL/CMOS

TTL/CMOS

Voltage

DAC

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.