CXA2000 datasheet(41/48 Pages) SONY

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CXA2000Q

5) C signal processing

The CVBS signal or chroma signal (specified input level: burst level of 300mVp-p) selected by the video switch

passes through the ACC, TOT, chroma amplifier and demodulation circuits, becomes the R-Y and B-Y color

difference signals, and is inverted for output on Pins 3 and 4. The color difference signals are averaged

together by the external 1H delay line, and are input to Pins 7 and 8. Both color difference signals are clamped

together with the Y signal input to Pin 5. They are then combined with the G-Y signal in the color control and

axis control circuits. After Y/C mixing, the signals become the RGB signals.

If the burst level goes to –35dB or less with respect to the specified input level, the color killer operates.

In addition, the color system (PAL/NTSC) and the subcarrier frequency (4.43MHz/3.58MHz) are automatically

identified according to the input chroma signal, and the internal VCO, demodulation circuit, axis control circuit,

etc., are adjusted automatically.

Furthermore, SECAM signals can also be identified if an external SECAM decoder is connected to Pin 1. In

this case, Pins 3 and 4 and the SECAM decoder color difference output are linked together directly, and

automatically one side goes to high impedance, the other goes to low impedance according to the input

chroma signal, and then they are input to the external 1H delay line.

System identification can be set to automatic or forced mode by the I2C bus (XTAL and COLOR SW). The

color system is output to the status register (COLOR SYS).

6) RGB Signal processing

The RGB signals obtained from the Y/C block pass through the half-tone switch circuit (YM SW), the two

switch circuits for the external RGB signals (YS1, YS2 SW), the picture control, dynamic color, gamma

compensation, clamp, brightness control, drive adjustment, cut-off adjustment and auto cut-off circuits, and are

output to Pins 22, 24 and 26.

The RGB signals input to Pins 12, 13, 14, 17, 18, and 19 are 100 IRE, 100% white 0.7Vp-p signals, in

accordance with the standard for normal video signals. If signals of 1.5Vp-p or more are input to Pins 17, 18,

and 19, 67 IRE output is obtained (digital input).

The voltage applied to Pin 28 (ABLIN) is compared with the internal reference voltage, integrated by the

capacitor which is connected to Pin 29, and performs picture control and brightness control.

In order to adjust the white balance (black balance), this IC has a drive control function which adjusts the gain

between the RGB outputs and a cut-off control function which adjusts the DC level between the RGB outputs.

Both drive control and cut-off control are adjusted by the I2C bus, with the Rch fixed and the G and Bch

variable. An auto cut-off function (AKB) which forms a loop between the IC and CRT and performs adjustment

automatically has also been added. This function can compensate for changes in the CRT with time. Auto cut-

off operation is as follows.

• R, G and B reference pulses for auto cut-off, shifted 1H each in the order mentioned, appear at the top of

the picture (actually, in the overscan portion). The reference pulse uses 1H in the V blanking interval, and

is output from each R, G and B output pin.

• The cathode current (Ik) of each R, G and B output is converted to a voltage and input to Pin 27.

• The voltage input to Pin 27 is compared with the reference voltage in the IC, and the current generated by

the resulting error voltage charges the capacitors connected to Pins 21, 23 and 25 for the reference pulse

interval and is held during all other interval.

• The loop functions to change the DC level of the R, G and B outputs in accordance with the capacitor pin

voltage so that the Pin 27 voltage matches the reference voltage in the IC.

The Rch for the reference voltage in the IC is fixed and the G and Bch are cut-off controlled by the I2C bus.

During G/B-CUTOFF center status, the loop functions so that the Rch for the reference pulse input to Pin 27 is

1Vp-p and the G and Bch are 0.81Vp-p.

The reference pulse timing can be varied by the I2C bus.

When AKB is not used, the IC can be set to manual cut-off mode with I2C bus settings. In this case, the DC

level of the R, G and B outputs can be varied by applying voltages independently to Pins 21, 23 and 25.

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