SM320C50EP

DIGITAL SIGNAL PROCESSOR

SGUS040A − AUGUST 2002 − REVISED JANUARY 2006

10

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

Tester Pin

Electronics

VLOAD

IOL

CT

IOH

Output

Under

Test

50

Ω

Where:

IOL

=

2.0 mA (all outputs)

IOH

=

300

µA (all outputs)

VLOAD =

1.5 V

CT

=

80 pF typical load circuit capacitance

Figure 1. Test Load Circuit

signal transition levels

Transistor-to-transistor logic (TTL) output levels are driven to a minimum logic-high level of 2.4 V and to a

maximum logic-low level of 0.6 V. Figure 2 shows the TTL-level outputs.

0.6 V

1 V

2 V

2.4 V

Figure 2. TTL-Level Outputs

TTL-output transition times are specified as follows:

at which the output is said to be low is 1 V.

at which the output is said to be high is 2 V.

Figure 3 shows the TTL-level inputs.

2.2 V

0.6 V

Figure 3. TTL-Level Inputs

TTL-compatible input transition times are specified as follows:

is 2 V, and the level at which the input is said to be low is 0.8 V.

is 0.8 V, and the level at which the input is said to be high is 2 V.