поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

STM32F051C6 датащи(PDF) 63 Page - STMicroelectronics

номер детали STM32F051C6
подробное описание детали  Low- and medium-density advanced ARM??based 32-bit MCU
PDF  104 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F051C6 датащи(HTML) 63 Page - STMicroelectronics

Back Button STM32F051C6 Datasheet HTML 59Page - STMicroelectronics STM32F051C6 Datasheet HTML 60Page - STMicroelectronics STM32F051C6 Datasheet HTML 61Page - STMicroelectronics STM32F051C6 Datasheet HTML 62Page - STMicroelectronics STM32F051C6 Datasheet HTML 63Page - STMicroelectronics STM32F051C6 Datasheet HTML 64Page - STMicroelectronics STM32F051C6 Datasheet HTML 65Page - STMicroelectronics STM32F051C6 Datasheet HTML 66Page - STMicroelectronics STM32F051C6 Datasheet HTML 67Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 63 / 104 page
background image
Electrical characteristics
STM32F051x
64/105
Doc ID 022265 Rev 3
6.3.8
PLL characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20.
6.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 41.
Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ @VDD
Max Unit
= 2.0 V
= 2.4 V
= 2.7 V
= 3 V
= 3.3 V
tWUSTOP
Wakeup from Stop
mode
Regulator in run
mode
4.24.2
4.24.2
4.2
5
µs
Regulator in low
power mode
8.05
7.05
6.6
6.27
6.05
9
tWUSTANDBY Wakeup from
Standby mode
60.35
55.6
53.5
52.02
50.96
tWUSLEEP
Wakeup from Sleep
mode
1.11.1
1.11.1
1.1
Table 42.
PLL characteristics
Symbol
Parameter
Value
Unit
Min
Typ
Max
fPLL_IN
PLL input clock(1)
1.
Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT.
1(2)
8.0
24(2)
MHz
PLL input clock duty cycle
40(2)
-60(2)
%
fPLL_OUT
PLL multiplier output clock
16(2)
-48
MHz
tLOCK
PLL lock time
-
-
200(2)
2.
Guaranteed by design, not tested in production.
µs
JitterPLL
Cycle-to-cycle jitter
-
-
300(2)
ps



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com