ThunderLAN

™ TNETE110A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996

16

POST OFFICE BOX 1443

switching characteristics, PCI 5-V and 3.3-V (see Note 15 and Figure 3 and Figure 4)

PARAMETER

MIN

MAX

UNIT

tVAL

Delay time, PCLK to bused signals valid (see Notes 16 and 17)†

2

11

ns

tVAL(PTP)

Delay time, PCLK to bused signals valid point-to-point (see Notes 16 and 17)

2

12

ns

ton

Float-to-active delay

2

ns

toff

Active-to-float delay

28

ns

† Characterized by design

NOTES: 15. Some of the timing symbols in this table are not currently listed with EIA or JEDEC standards for semiconductor symbology but are

consistent with the PCI Local-Bus Specification, Revision 2.0.

16. Minimum times are measured with a 0-pF equivalent load; maximum times are measured with a 50-pF equivalent load. Actual test

capacitance may vary, but results should be correlated to these specifications.

17. PREQ and PGNT are point-to-point signals, and have different output valid delay and input setup times than do bused signals. PGNT

has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused.

timing requirements, PCI 5-V and 3.3-V (see Note 15 and Figure 4)

MIN

MAX

UNIT

tsu

Setup time, bused signals valid to PCLK (see Note 17)

7

ns

tsu(PTP)

Setup time to PCLK—point-to-point (see Note 17)

10, 12

ns

th

Input hold time from PCLK

0

ns

tc

Cycle time, PCLK (see Note 18)

30

500‡

ns

tw(H)

Pulse duration, PCLK high

12

ns

tw(L)

Pulse duration, PCLK low

12

ns

tslew

Slew rate, PCLK (see Note 19)‡

1

4

V/ns

‡ Specified by design and system specification.

NOTES: 15. Some of the timing symbols in this table are not currently listed with EIA or JEDEC standards for semiconductor symbology but are

consistent with the PCI Local-Bus Specification, Revision 2.0.

17. PREQ and PGNT are point-to-point signals, and have different output valid delay and input setup times than do bused signals. PGNT

has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused.

18. As a requirement for frame transmission /reception, the minimum PCLK frequency varies with network speed. The clock may only

be stopped in a low state.

19. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum

peak-to-peak portion of the clock waveform.