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TNETE110PM датащи(PDF) 22 Page - Texas Instruments

номер детали TNETE110PM
подробное описание детали  PCI ETHERNETE CONTROLLER SINGLE-CHIP 10 BASE-T
PDF  26 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI1 - Texas Instruments

TNETE110PM датащи(HTML) 22 Page - Texas Instruments

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ThunderLAN
™ TNETE110PM
PCI ETHERNET
™ CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS029 – SEPTEMBER 1996
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
switching characteristics for configuration EEPROM interface (see Figure 8)
PARAMETER
MIN
MAX
UNIT
fCLK(EDCLK)
Clock frequency, EDCLK
0
100
kHz
td(EDCLKL-EDIOV)
EDCLK low to EDIO data in valid
0.3
3.5
µs
td(EDIO free)
Time the bus must be free before a new transmission can start
4.7
µs
td(EDIOV-EDCLKL)
Delay time, EDIO valid after EDCLK low (start condition hold time for EEPROM)
4
µs
tw(L)
Low period, clock
4.7
µs
tw(H)
High period, clock
4
µs
td(EDCLKH-EDIOV)
Delay time, EDCLK high to EDIO valid (start condition setup time)
4.7
µs
td(EDCLKL-EDIOX)
Delay time, EDCLK low to EDIO changing (data out hold time)
0
µs
td(EDIOV-EDCLKH)
Delay time, EDIO valid to EDCLK high (data out setup time)
250
ns
tr
Rise time, EDIO and EDCLK
1
µs
tf
Fall time, EDIO and EDCLK
300
ns
td(EDCLKH-EDIOH)
Delay time, EDCLK high to EDIO high (stop condition setup time)
4.7
µs
td(EDCLKL-EDIOX)
Delay time, EDCLK low to EDIO changing (data in hold time)
300
ns
td(EDCLKH-EDIOV)
EDCLK
EDIO (OUT)
EDIO (IN)
td(EDIOV-EDCLKL)
tf
td(EDCLKL-EDIOV)
tw(H)
tw(L)
td(EDCLKL-EDIOX)
td(EDIOV-EDCLKH)
td(EDCLKL-EDIOX)
tr
td(EDCLKH-EDIOH)
td(EDIO free)
Figure 8. Configuration EEPROM Interface Timing



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