ThunderLAN

™ TNETE110

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS018B – MARCH 1995 - REVISED MAY 1996

22

POST OFFICE BOX 1443

MIN

TYP

MAX

UNIT

td(VDDH - FXTL1V)

Delay time, minimum VDD high level to first valid FXTL1 full swing period

(see Note 21)

100

ms

tw(H)

Pulse duration, FXTL1 high

13

ns

tw(L)

Pulse duration, FXTL1 low

13

ns

tt

Transition time, FXTL1

7

ns

tc

Cycle time, FXTL1

50

ns

Tolerance of FXTL1 input frequency

"0.01

%

† The FXTL signal can be implemented by either connecting a 20-MHz crystal using the FXTL1 and FXTL2 pins or by driving the FXTL1 from a

20-MHz crystal oscillator module.

NOTE 21: This specification is provided as an aid to board design. This specification is not assured during manufacturing testing.

FXTL1

VDD

td(VDDH - FXTL1V)

Minimum VDD High Level

tc

tw(H)

tw(L)

tt

tt

Figure 9. Crystal Oscillator Timing