CDCVF2505

3.3V CLOCK PHASELOCK LOOP CLOCK DRIVER

SCAS640E − JULY 2000 − REVISED MARCH 2005

2

POST OFFICE BOX 655303

FUNCTION TABLE

INPUT

OUTPUTS

CLKIN

1Y (0:3)

CLKOUT

L

H

<10 MHz†

L

H

Z

L

H

Z

† Typically, below 2 MHz the device goes in power-down mode in

which the PLL is turned off and the outputs enter into Hi-Z mode. If

a >10-MHz signal is applied at CLKIN the PLL turns on, reacquires

lock, and stabilizes after approximately 100

µs. The outputs will then

be enabled.

functional block diagram

Edge Detect

Typical <10 MHz

Power Down

3-State

1

8

3

2

5

7

CLKOUT

1Y0

1Y1

1Y2

1Y3

CLKIN

PLL

25

Ω

25

Ω

25

Ω

25

Ω

25

Ω