поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

TNETX3110 датащи(PDF) 54 Page - Texas Instruments

номер детали TNETX3110
подробное описание детали  ThunderSWITCHE 8/3 ETHERNETE SWITCH WITH EIGHT 10-MBIT/S PORTS AND THREE 10-/100-MBIT/S PORTS
PDF  65 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI1 - Texas Instruments

TNETX3110 датащи(HTML) 54 Page - Texas Instruments

Back Button TNETX3110 Datasheet HTML 50Page - Texas Instruments TNETX3110 Datasheet HTML 51Page - Texas Instruments TNETX3110 Datasheet HTML 52Page - Texas Instruments TNETX3110 Datasheet HTML 53Page - Texas Instruments TNETX3110 Datasheet HTML 54Page - Texas Instruments TNETX3110 Datasheet HTML 55Page - Texas Instruments TNETX3110 Datasheet HTML 56Page - Texas Instruments TNETX3110 Datasheet HTML 57Page - Texas Instruments TNETX3110 Datasheet HTML 58Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 54 / 65 page
background image
TNETX3110
ThunderSWITCH
™ 8/3 ETHERNET™ SWITCH
WITH 8 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS047A – MARCH 1998 – REVISED APRIL 1999
54
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
10-/100-Mbit/s transmit ports (08, 09, and 10)
timing requirements (see Figure 14)†
NO.
MIN
MAX
UNIT
1
tc(MxxTCLK)
Cycle time, MxxTCLK
25
25
ns
2
tw(MxxTCLKL)
Pulse duration, MxxTCLK low
ns
3
tw(MxxTCLKH)
Pulse duration, MxxTCLK high
14
ns
† xx = ports 08, 09, and 10
operating characteristics over recommended operating conditions (see Note 8 and Figure 14)†
NO.
PARAMETER
MIN
MAX
UNIT
4
td(MxxTXD)
Delay time, from MxxTCLK
↑ to MxxTXD3–MxxTXD0 valid
0
25
ns
4
td(MxxTXEN)
Delay time, from MxxTCLK
↑ to MxxTXEN valid
0
25
ns
4
td(MxxTXER)
Delay time, from MxxTCLK
↑ to MxxTXER valid
0
25
ns
† xx = ports 08, 09, and 10
NOTE 8: Both MxxCRS and MxxCOL are driven asynchronously by the PHY. MxxTXD3–MxxTXD0 is driven by the reconciliation sublayer
synchronous to the MxxTCLK. MxxTXEN is asserted and deasserted by the reconciliation sublayer synchronous to the MxxTCLK rising
edge. MxxTXER is driven synchronous to the rising edge of MxxTCLK.
4
MxxTXD3–MxxTXD0
MxxTXEN
MxxTXER
(outputs)
MxxTCLK
(input)
2
3
1
Figure 14. 10-/100-Mbit/s Transmit Ports



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com