TLV704xx

SBVS148C

– OCTOBER 2010 – REVISED AUGUST 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

XX is nominal output voltage (for example 33 = 3.3 V)

TLV704xxyyyz

YYY is Package Designator

Z is Package Quantity

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range, unless otherwise noted.

VALUE

UNIT

MIN

MAX

IN

–0.3

24

V

Current source

OUT

Internally limited

–40

+150

°C

Temperature

–65

+150

°C

Human body model (HBM)

2

kV

QSS 009-105 (JESD22-A114A)

Charge device model (CDM)

500

V

QSS 009-147 (JESD22-C101B.01)

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2)

All voltages are with respect to network ground terminal.

(3)

ESD testing is performed according to the respective JESD22 JEDEC standard.

THERMAL INFORMATION

TLV70433DBV

DBV

UNITS

5 PINS

Junction-to-ambient thermal resistance

213.1

Junction-to-case (top) thermal resistance

110.9

Junction-to-board thermal resistance

97.4

°C/W

Junction-to-top characterization parameter

22.0

Junction-to-board characterization parameter

78.4

Junction-to-case (bottom) thermal resistance

n/a

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

POWER DISSIPATION RATING TABLE

BOARD

PACKAGE

RATING

RATING

RATING

DBV

213.1

°C/W

470 mW

258 mW

188 mW

(1)

The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch

× 3-inch, multilayer board with 1-ounce internal power

and ground planes and 2-ounce copper traces on top and bottom of the board.

2

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